Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-07-22
2001-05-01
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S094000
Reexamination Certificate
active
06226222
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a synchronous semiconductor memory, and more particularly to a technique for controlling sense amplifiers employed in a synchronous memory device responding to an external clock signal.
BACKGROUND OF THE INVENTION
It is well known that address transition detection circuits are widely used in semiconductor memories, e.g., read only memories, in order to control internal accessing circuits (e.g. sense amplifier circuits) in an appropriate processing timing, which enhances a sensing speed for stored data and actuates a generation of plural control signals. An address transition detection circuit senses a variation of an external address signal and then generates a master signal informing the address transition. All of control signals employed in performing a sensing operation in a memory device are made from using the master signal, e.g., delaying therefrom or combining therewith, generated from the address transition detection circuit. The ATD-oriented control signals with their own pulse widths and delaying terms between them, independently of an external operating frequency, are fixed into constant values, once after being manufactured, in accordance with a demand of a circuit designing.
In a sensing operation of a read only memory, as one sensing cycle which designates the period from beginning of the sensing operation to latching a result of the sensing is always constant, it would be possible to select a weak cell or to latch distorted sensing data nevertheless of a later sensing timing due to a power noise or a timing variation. Such mis-matched phenomena between the control signals and sensing cycle time causes the yield of a memory device to be reduced. And, a new demand for a sensing time shorter than a designed specification for a sense amplifier might need a newly modified circuit for the address transition detection.
For the purpose of enhancing an operating frequency of an asynchronous memory device, a synchronous memory has been regarded to as an useful way in a high bandwidth memory operation. Since the synchronous memory performs internal operations in response to a system clock which has a predetermined pulse width and frequency and the system clock is assigned to one of several frequency options, the control for the sense amplifiers must be designed to be cooperated with a frequency out of the system clocks.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a synchronous read only memory having a circuits for controlling a sensing operation in accordance with a clock signal which has a constant cycle.
It is another object of the invention to provide a synchronous read only memory having a circuit for controlling a sensing operation over which various clock frequencies are adapted.
It is another object of the invention to provide a synchronous read only memory having a circuit for controlling a sensing operation in various clock frequency conditions, according to predetermined latency informations which correspond to the clock frequency conditions.
In order to accomplish those objects, a read only memory includes a clock signal source, the clock signal having constantly oscillated pulse periods, a sense amplifier operated by a plurality of control signals, a latch circuit coupled to an output of the sense amplifier, and a circuit for generating the control signals and for generating a control signal which is applied to the latch circuit, in response to an information corresponding to the pulse period of the clock signal.
Another aspect of a read only memory includes a clock signal source, the clock signal having constantly oscillated pulse periods, a sense amplifier operated by a plurality of control signals, a latch circuit coupled to an output of the sense amplifier, and a circuit for generating the control signals and for generating a latch control signal which is applied to the latch circuit, the sense amplifier control signals being generated in response to an latency information corresponding to the pulse period of the clock signal in a specific frequency condition and the latch control signal being generated in response to an latency counting signal in the specific frequency conditions. The generating circuit is comprised of at least a selection switch which determines a delaying state of the control signal in response to the latency information signal. The specific frequency condition is when one sensing cycle time of the sense amplifier is longer than that of the pulse period of the clock signal.
Another aspect of the invention is a read only memory including: a master signal source, the master signal being generated when an address signal is changed; a clock signal source, the clock signal having constantly oscillated pulse periods; a sense amplifier operated by a plurality of sense amplifier control signals; a latch circuit coupled to an output of the sense amplifier; a first circuit for generating a first control signal of the sense amplifier control signals; a second circuit for generating a second control signals of the sense amplifier control signals, the second control signal being generated in response to an latency information corresponding to the pulse period of the clock signal in a specific frequency condition; a third circuit for generating a latch control signal which is applied to the latch circuit, the latch control signal being generated in response to an latency counting signal in the specific frequency condition; and a fourth circuit for generating a third control signal of the sense amplifier control signals, the third control signals being activated in response to the master signal and being disabled in response to the latch control signal. In this embodiment, each of the second and third circuits has a selection switch which determines a delaying state of each of the control signals in response to the latency information signal.
REFERENCES:
patent: 5793665 (1998-08-01), Kim et al.
patent: 5986918 (1999-11-01), Lee
patent: 6031770 (2000-02-01), Pawlowski
Myers Bigel & Sibley & Sajovec
Phan Trong
Samsung Electronics Co,. Ltd.
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