Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-06-03
2001-07-03
Marcelo, Melvin (Department: 2663)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C340S928000
Reexamination Certificate
active
06256325
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C §119 from an application entitled Transmission Apparatus For Half Duplex Communication Using HDLC earlier filed in the Korean Industrial Property Office on Jun. 4, 1997, and there duly assigned Ser. No. 97-23166 by that Office.
FIELD OF THE INVENTION
The present invention relates to a transmission apparatus for half duplex communication using high level data link control (HDLC), specifically, to a transmission apparatus for half duplex communication using HDLC, which enables reliable communications between a lane-installed radio frequency communication controller (RFC) and a vehicle-attached controller using back scattering method in an electronic toll collecting system (ETCS) which is an important part of an intelligent transmission system.
BACKGROUND OF THE INVENTION
Dedicated short range communication (DSRC) using 5.8 GHz of frequency is being widely used in an electronic toll collecting system, and especially adopted as a standard in European countries. An exemplary electronic toll collecting system is constructed in such a manner that a radio frequency communication controller is installed in a tollgate for each lane of a toll road. An on-board unit for communicating with the radio frequency communication controller is attached to a vehicle. This system employs a back scattering communication technique so as to simplify the configuration of the on-board unit. Accordingly, communications are performed in a half duplex communication mode, and an HDLC protocol is used as a data link layer to carry out reliable communication between the on-board unit passing a narrow communication area and radio frequency communication controller.
The transmission unit in a HDLC protocol is called a “frame” which includes an address field, control field and information field. The address field is used to indicate the address of a transmitting part or a receiving part, and the control field is used for various monitoring and controlling operations. The information field is a portion where actual information messages enter, and its length may be optional. Before and after the frame, flags are inserted in order to display the initiation and the completion of a frame and maintain the settlement of synchronization. The flag is fixed in an 8-bit specific pattern, for example, 01111110
2
(7EH). The radio frequency communication controller, or on-board unit, can recognize the initiation or the completion of the frame, on finding the flag bit pattern, since only the flag portion in the transmitted data is fixed.
In the above system, the radio frequency communication controller plays a main role in communications in such a way that, if the on-board unit responds to a response request signal sent from the radio frequency communication controller, a transaction is finished according to a predetermined communication sequence, and if not, the radio frequency communication controller transmits the response request signal in a specific cycle. Since the system uses the back scattering method, only a carrier wave is allowed to be transmitted to the on-board unit during a period when the radio frequency communication controller does not transmit data. Here, efficient high-speed communication can be realized only when the amount of data transmitted/received between the radio frequency communication controller and the on-board unit is minimized to reduce the time required for the communication. Furthermore, in order to allow the reception part to stably recover data, it is required that the data be coded using a code system having clock information, such as Manchester code or frequency modulation
0
(FM
0
) code, and it is transmitted in the form of flag-flag-frame-flag-flag, where at least two flags are guaranteed.
One method for satisfying the aforementioned minimum condition is a method in which a central processing unit (CPU) included in the radio frequency communication controller drives an HDLC controller at a predetermined time before the actual frame will be transmitted, to transmit a flag, and then the frame is transmitted after the lapse of time calculatively obtained. In this technique, a flag following the frame is also transmitted by the same manner. There is another method in which data are made in the form of flag-flag-frame-flag-flag according to a software program, and then transmitted through the HDLC controller, without forming the flag by using the HDLC controller.
The former method has a problem in exact transmission of two flags because of nonsynchronization between a time required for the CPU to wait and a flag transmitting time. Furthermore, if the transmission speed is changed, normal communication needs to modify the program.
Moreover, when a general HDLC controller is employed, the impedance of its output port should be continuously switched according to whether data is transmitted or not, because the radio frequency communication controller is required not to transmit other data after the transmission of predetermined data, which impedes the rapid communications.
Meanwhile, though the latter technique where the flags are inserted into the frame is conceptionally easy to perform, the reception part cannot recognize the flags because the general HDLC controller has a zero insertion function which compulsorily inserts ‘0’ when five ‘1’s or more occur continuously. Accordingly, there is a problem wherein normal communications are not able to be carried out.
SUMMARY OF THE INVENTION
Therefore, in order to overcome the above mentioned drawbacks, an objective of the present invention is to provide a transmission apparatus for half duplex communication using HDLC, in which a simple logic circuit is added to a HDLC controller to transmit a frame, adding flags before and after the frame all the time, without modification of a program even when a transmission speed is changed, thereby enabling rapid and reliable communications.
To accomplish the objective of the present invention, there is provided a transmission apparatus for half duplex communication using HDLC, including: means for generating a clock (TxC), to supply the clock to each section of the apparatus as a synchronous clock; an HDLC controller for continuously outputting a flag signal in a predetermined bit pattern while it does not transmit a frame signal; flag delay/detection means for outputting with delaying an output (TxD) of the HDLC controller by one byte, and outputting a flag detection signal (/Flag_detect) whenever the flag signal is detected; a CPU for outputting a transmission request signal (/Tx_Req) during a period determined with relation to the magnitude of the frame signal when data transmission is required, and sending the frame signal to the HDLC controller after a transmission ready signal (/Tx_Ready) is received; control logic means for synchronizing the transmission request signal (/Tx_Req) with the flag detection signal (/Flag_detect) subsequently generated, to generate the transmission ready signal (/Tx_Ready), and simultaneously, to output a transmission enable signal (/Tx_Enable) determining a transmission enable time, thereby adding a desired number of flag signals (Flag) before and after the frame signal; and output control means for sequentially encoding signals output from the HDLC controller in a predetermined code system, and outputting the encoded signals during an active time of the transmission enable signal (/Tx_Enable).
In the above configuration, the flag delay/detection means include an 8-bit shift register for shifting the output (Tx/D) of the HDLC controller, and an 8-bit comparator for judging whether the contents of the shift register correspond to the flag signal or not, and then generating the flag detection signal (/Flag_detect) when the contents of the shift register correspond to the flag signal.
The control logic menas include a first D-flip-flop for synchronizing the transmission request signal (/Tx_Req) with the flag detection signal (/Flag_detect), to
Bushnell , Esq. Robert E.
Kwoh Jasper
Marcelo Melvin
Samsung Electronics Co,. Ltd.
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