Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2000-08-03
2001-07-03
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189040
Reexamination Certificate
active
06256249
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory devices generally and, more particularly, to a method for integrating a refresh cycle and a read data/write-back data cycle of a dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a diagram illustrating a conventional dynamic random access memory (DRAM)
10
is shown. The conventional DRAM preserves data during periodic absences of power by implementing a memory cell
12
as a capacitor
14
and an access transistor
16
. The conventional DRAM uses a single memory cell
12
for each bit of data stored. A sense amplifier
18
compares a signal received from the memory cell
12
via a bitline
20
with a reference signal REF to determine a stored value. The memory cell
12
is accessed using a single wordline
22
.
Since the charge on the capacitor
14
will slowly leak away, the cells need to be “refreshed” once every few milliseconds. In order to refresh the cells, the DRAM typically requires an additional cycle. During the normal cycle, the DRAM will read data and write-back data. During a refresh cycle, the DRAM will (i) read data and write-back data as in the normal cycle and (ii) perform another read that is not intended for user access but rather to refresh the read data to prevent degradation. While effectively preserving the data, the additional refresh cycle makes the DRAM slower than a static random access memory (SRAM).
A static random access memory (SRAM) has only one cycle during which the chip either reads data or writes data. The SRAM is generally faster than other types of memory that require multiple cycles. Static random access memory requires more die space and must be constantly powered to maintain stored data.
It would be desirable to have a DRAM that could be refreshed at the same time as a normal access regardless of where the data is to be refreshed or the data to be accessed is stored.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a memory and a logic circuit. The memory may comprise a plurality of storage elements configured to read and write data in response to a first internal address signal and a second internal address signal. The logic circuit may be configured to generate either (i) the first and the second internal address signals when accessing one of the storage elements for a read or a write operation or (ii) the first internal address signal when accessing one of the storage elements for a read refresh operation.
The objects, features and advantages of the present invention include providing a method and/or apparatus for increasing the performance of a DRAM chip by incorporating the refresh cycle into the read data/write-back data cycle.
REFERENCES:
patent: 4112513 (1978-09-01), Elsner
patent: 4203159 (1980-05-01), Wandlass
patent: 4758993 (1988-07-01), Takemae
patent: 4879692 (1989-11-01), Tokusnige
patent: 4914630 (1990-04-01), Fujishima
patent: 5291443 (1994-03-01), Lim
patent: 6134169 (2000-10-01), Tanaka
patent: 6154409 (2000-11-01), Huang
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Nguyen Tan T.
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