Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-26
2001-10-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S106000
Reexamination Certificate
active
06300234
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally related to processes for forming electrical devices and more particularly to processes for forming electrical devices where a film or tape is applied to a substrate as part of an operation to form conductors to the substrate.
RELATED ART
In the production of electronic devices, semiconductor wafers typically either go through a wire bond final assembly or a bump final assembly in order to make circuit interconnections. Bump final assembly is an interconnect technology, also known as “flip chip,” in which a chip is fabricated with the circuitry facing the packaging substrate and in which the chip is flipped over to match patterned solder bumps on the chip with a corresponding pattern on the packaging substrate. Solder bumps, deposited through a bump mask onto wettable chip pads thus connect to matching wettable packaging substrate pads. The flipped chips must be aligned to corresponding packaging substrate metal patterns, and then electrical and mechanical interconnects are formed simultaneously by reflowing the solder bumps. Bumped wafers currently undergo a mask alignment process in which a shadow mask is manually aligned using stainless steel top and bottom fixtures. This fixture is then maintained through the majority of the process. After mask alignment, a dry etch is performed, which is typically an argon plasma cleaning to remove any heavy oxides on the bond pads and allow for a better attachment of the base metals. Following dry etch, the wafer is subjected to an evaporation high vacuum metal deposition in which the pad limiting metal (PLM) is deposited. For typical CMOS technology, the PLM includes chrome, copper, and gold. Following the PLM deposition, a lead/tin deposition is performed, usually a composite of 97% lead and 3% tin, which forms the solder bump. Following the lead/tin deposition, the fixture is then removed, the mask is taken off and the built-up evaporated materials directly over the top of the bond pads remains. The solder material resembles a truncated cone at this point. The solder is then re-flowed to form the final bump.
The fixture used for the evaporative bump process described above is a molybdenum mask fixture between two stainless steel ring sets with a wafer in between. Disadvantages of the use of this type of mask include the expense of making and maintaining the stainless steel fixtures. After the masks are etched, they may be reused multiple times but tend to get damaged through the manual processing of the wafers. Each mask is expensive, and in a typical production situation, approximately 800 masks per device may be required. In addition, each mask must be sent out to be cleaned after use, typically requiring a large inventory so that half may be cleaned while the other half are being used in processing devices.
Another disadvantage of using this type of shadow mask is the alignment process itself. The alignment process is extremely manual and has a high degree of error. The process consists of cameras, focused on various positioning holes on the mask and coordinating features on the wafer, that an operator manually adjusts in X, Y and Theta positions until the best fit is achieved. The alignment is also difficult because the mask is thermally compensated so that, while the alignment is performed at ambient temperature, the bumps must align with the bond pads at the higher temperature of processing. Therefore, any variation in the initial alignment can cause a further misalignment after thermal expansion of the mask during processing.
Still another limitation of the current mask technology is the size and pitch of solder bumps that can be achieved. Because of the etch process, the thickness of the mask is dependent on the aperture size (the diameter of the bump). For example, a mask for a 100 micron opening is generally about 3.8 mils thick, and as the aperture size decreases, the mask must be thinner, which makes it more susceptible to damage during processing. Yet another limitation is the pitch, or spacing between bumps. For current shadow mask technology, the lower limits are 100 micron bumps on a 225 micron pitch. Smaller pitches may cause an underspray problem because the mask may be more flexible and may deform or lift up from the wafer allowing underspray and causing a short in the device.
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B.P. Richards et al., “Lead-Free Soldering”, Department of Trade and Industry (dti), Report “Analysis of the Current Status of Lead-Free Soldering”, 60 pgs.
Motorola C4 Product Design Manual, 1993, vol. I: Chip and Wafer Design, Chapter 1—Technology Overview, Issue A, pp. 1-11 and 8-1-8-2.
E. Jan Vardaman et al., “The Lead-Free Movement: Environmentally Friendly Electronics Manufacturing”, TechSearch Int'l. Inc., Technology Licensing & Consulting, pp. 1-79.
Argento Christopher W.
Flynn Todd M.
Larsen Larry J.
Meyer George R.
Motorola Inc.
Nelms David
Nhu David
Rodriguez Robert A.
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