Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-10-15
2001-12-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06330705
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to remodeling, designing and editing method and system for a printed wiring board in which the latest circuit data can be reflected by performing a wire disconnection or wiring by the use of jumper (hereinafter it is called jumper-wiring) on a previously provided printed wiring board to modify its circuit design, packaged on one component of a CAD system, i.e., a computer aided design system.
2. Description of the Related Art
It has been extended to design for packaging a printed wiring board by employing a CAD system, i.e., computer aided design system, on one component.
In addition, there is a case where alternation of a packaged board is required on the previously provided printed circuit board due to modification or mis-designing of the circuit design. In this case, a remodeling, designing and editing method and system for a printed wiring board has been employed. In this method and system, the packaged CAD is used to edit and update the circuit design data.
On the other hand, there is a demand to easily execute actual editing operations at high speed when modifying the circuits on the previously provided printed wiring board with respect to a multi-layered or high-density, printed wiring board or a high-speeded circuit.
FIG. 10
shows one example of the conventional remodeling, designing and editing method and system for a printed wiring board. Pattern data, such as a via-hole VIA (hereinafter, it is called as a via for simplicity), which is a circuit pattern when creating a printed wiring board on the data base
1
, data of the latest circuit on one printed wiring board to which altered sections are supplied, and remodeling data, such as data of disconnection or jumper-wiring when the alternation is executed by wiring disconnection or jumper-wiring, are stored in a database
1
.
Additionally, the system of
FIG. 10
comprises an editor
2
for remodeling, designing, and editing a printed wiring board having a display device. A controller in the editor
2
executes an automatic remodeling program
3
to activate an editing and checking controller
4
. Then, the display controller
5
controls to display the result on the display device.
A remodeling, designing and editing method on the conventional system will be now explained.
FIG. 11
is a structural example of layers on a multi-layered printed wiring board. In this example, the board includes eight layers L
1
to L
8
. The third layer L
3
is an electric source, and the sixth layer L
6
is an earth layer, both of which surfaces are conductive. The other layers are signal layers. The first layer L
1
is for a component plane, and the sixth layer is for a soldering plane.
In this example, when the circuit is modified by disconnecting a wire, it is possible to respectively disconnect the first and second layers L
1
and L
2
from the component plane side, and the eighth and seventh layers L
8
and L
7
from the soldering plane side by radiating a laser beam. Since the fourth and fifth layers L
4
and L
5
may be through the conductive layers L
3
and L
6
, it is impossible to disconnect these layers L
4
and L
5
even by radiating the laser beam.
A previously designed circuit pattern, as shown in
FIG. 12
, in the structure for a multi-layered printed wiring board will be now considered. That is, the circuit of
FIG. 12
has a connection pattern of A-B-C-D. V
1
and V
2
are vias of the printed wiring board. In
FIG. 12
, L
1
, L
2
, L
5
, L
8
are connections of the corresponding signal layers. Therefore, the circuit pattern of
FIG. 12
forms a packaging connection structure shown in FIG.
13
.
The connection pattern A-B-C-D of the multi-layered printed wiring board is modified to A-B-D as data of the latest connection pattern. Therefore, the patterns A-B-C-D and A-B-C are respectively stored as the previously provided pattern data and data of the latest connection pattern in the database
1
.
The editing and checking controller
4
compares these patterns. The editor
2
displays the result, such as a circuit pattern shown in
FIG. 12
, under the control of the display controller
5
. In this example, a part of the pattern of
FIG. 12
can be enlarged and displayed by a designer's instruction from a mouse.
In
FIG. 12
, the different point between the previously provided connection pattern and the latest connection pattern is a connection between a via V
2
and C. This difference is called an error, hereinafter. Accordingly, the error between the via V
2
and C is emphasized by displaying a wire L
5
by a bold line, or displaying it with a specified color, for example.
Accordingly, the designer detects the error-emphasized section with his own eyes and inputs a disconnecting instruction on the editor
2
. Then, the designer should consider reducing the number of disconnecting instructions.
In this example, the editing and checking controller
4
can edit two layers, concurrently, in order to avoid from complication of editing. Therefore, a designer should consider a disconnection processing between V
2
and C belonging to the error-displayed section for editing L
1
and L
8
layers in order to reduce the number of the disconnecting instructions at first. However, a connection between V
2
and C is belonging to the L
5
layer, and this connection can not be edited. Therefore, L
1
and L
5
layers are used for editing. However, the L
5
layer, to which the connection between V
2
and C is belonging, can not be disconnected as explained above.
Accordingly, the editing and checking controller
4
informs the disability of disconnection to the designer. Therefore, the designer moves the enlarged and displayed section by a mouse to obtain a section where an error is not emphasized to be edited. The designer sees the disconnected section line and selects L
2
and L
8
layers to be edited. Then, the designer instructs a disconnection between V
2
and V
1
, and further instructs a disconnection between V
2
and D.
After that, the designer instructs wiring between V
1
and D, now shown in the diagram. Thereby, the pattern is modified to a connection pattern of A-B-D.
The database
1
stores disconnection data between V
2
and V
1
and jumper-wiring data between V
1
and D as remodeling data.
Further,
FIGS. 14A
,
14
B and
14
C are explanatory diagrams for editing when remodeling a circuit pattern by adding, deleting or moving components in the system of FIG.
10
. In
FIG. 14A
, components I
10
and I
20
are provided on a previously designed printed wiring board. A display sample of “STEP
1
” is displayed on the editor
2
. Then, a designer instructs to delete the component I
10
.
As a result, an image of the component I
10
is not displayed, and only lands are displayed, as shown in a display sample of STEP
2
, under the control of the display controller
5
.
Additionally,
FIG. 14B
shows editing processing when a component I
30
is newly added to an idle space of the printed wiring board on the display example STEP
1
. The board on the STEP
2
shows an example where the designer instructs to arrange the component I
30
on a position of a space I. The board of the STEP
3
shows an example where the designer instructs to add the component I
30
on a position of the previously provided component R
10
.
In this case, if there is no land on the position where the designer instructs to add the new component, i.e., STEP
2
of
FIG. 14B
, this circuit cannot be remodeled, and therefore, this instruction is refused by the editing and checking controller
4
. Further, the component R
10
is arranged on a position where the designer instructs to add the new component. In other words, different components are overlapped and located on the same land on STEP
3
of FIG.
14
B. Similarly to the above-described case, the editing and checking controller
4
refuses this instruction.
Further, if a designer instructs to move the component I
10
, the land on the original position can not be displayed after moving the component, as shown in STEP
2
Kobayashi Chikou
Matsushita Hideharu
Taoka Shinichi
Fujitsu Limited
Garbowski Leigh Marie
Rosenman & Colin LLP
Smith Matthew
LandOfFree
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