Programmable logic device with logic signal delay...

Details Programmable logic device with logic signal delay... Programmable logic device with logic signal delay...

2000-07-26

2001-12-04

Lam, Tuan T. (Department: 2816)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S149000, C327S158000

Reexamination Certificate

active

06326812

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to integrated circuits and more particularly to the distribution of clock signals in programmable logic devices.
2. Description of the Related Art
A programmable logic device (PLD) integrated circuit comprises an array of functional blocks along with an interconnection network. The specific function of each block and the connections between blocks can be programmed by the user. For example, a typical PLD generally includes a control store in the form of a static random access memory array (SRAM), for instance, and includes functional units and interconnect wires that are programmed by writing to the control store to establish specific logic gates, storage elements and interconnect paths.
As PLDs increase in logic density, clock distribution delay becomes an increasingly significant fraction of the clock period. This clock distribution delay can impact device performance by degrading setup, hold and clock-to-output parameters, for example. Moreover, race conditions between clocks and data can result in race-through problems if proper clock planning techniques are not applied. A typical PLD often provides a variety of alternative clock sources. A PLD register, for instance, may be programmable to receive a clock signal from any of multiple different clock sources. Clock tree networks have been used to model clock delays around PLDs in order to reduce clock skew problems. Specifically, delays may be added to clock nets that have shorter clock paths so that they will match the delays experienced by the larger clock nets. This approach has been used to equalize the clock delays in such earlier PLDs.
Phase lock loop (PLL) circuits have been added to PLDs to generate clock signals with minimal clock skew and delay problems and improved setup and clock-to-output times. For instance, a PLL circuit may be coupled to receive an external reference clock signal applied to a clock pad of the PLD and to produce a duplicate version of the reference clock signal (same frequency) which is earlier in phase relative to the reference clock signal. This has been achieved by tapping a delay element in the feedback path of the PLL circuit so as to provide a PLL clock signal which is an early version of the external reference clock signal.
PLDs have been implemented in which a PLL has such a delay network in its feedback path that models the PLD clock tree so as to track over process, temperature and voltage to provide a consistent clock skew with respect to the reference clock. Such a delay network causes the PLL to generate an early clock that is ahead of the reference clock by an amount that compensates for the delay of the clock network. In this manner, chip clock skew can be canceled, and local clock drivers that propagate the PLL early clock can have relatively little clock skew with respect to the reference clock signal.
The drawing of
FIG. 1
is a generalized schematic block diagram which shows a clock distribution network
20
employed in an earlier FLEX 10K programmable logic device which is presented merely as an illustrative example of the related art. Details of the FLEX 10K PLD can be found in the Altera 1996 Data Book produced by the Altera Corporation of San Jose Calif. The clock distribution network of the PLD includes a clock pad
22
which receives an external clock signal. The reference clock signal is distributed about the device by a reference clock conductor path
24
. The clock distribution network also includes a phase lock loop
26
which receives the reference clock signal via a driver circuit
28
and has a clock network delay compensation circuit in its feedback path which is tapped to produce an early (or leading) version of the reference clock signal which shall be referred to as the early PLL clock signal. The early PLL clock signal is distributed about the device by a PLL clock conductor path
30
. The clock distribution network is divided into six localized sections. Four sections
32
-
1
,
32
-
2
,
32
-
3
and
32
-
4
provide clock signals to registers in the PLD periphery which latch data on external input/output pads (not shown). Two sections
34
-
1
and
34
-
2
provide clock signals to registers in the PLD core (details not shown) which is programmable to build logic functions. The clock network is constructed so that the delays remain substantially constant regardless of the manner in which the periphery and the core are programmed.
Each of the respective six sections of the clock distribution network
20
shown in
FIG. 1
includes a respective clock selection circuit
38
which receives as inputs the reference clock signal and the early PLL clock signal. The reference clock signal is conducted along the reference clock conductor path and is provided to respective selection circuits via respective driver circuits. The early PLL clock signal is conducted along the early PLL clock conductor path
24
and is provided to respective selection circuits via respective local delay elements
40
which may be programmable.
The local delay elements, which are part of the clock distribution network, are balanced so that all of the respective selection circuits receive PLL clock signals that are in phase with each other and that are in phase with the reference clock signal received on the external pad. A larger local delay d
1
is produced by the delay local elements
40
that are closer to the reference clock pad and the PLL since the distance traveled by the early PLL clock signal is shorter. Conversely, a shorter local delay d
3
is produced by the local delay elements
44
that are farther from the reference clock pad and the PLL since the distance traveled by the early PLL clock signal is longer. Thus, the local delays impart different delay amounts at different locations in the clock signal distribution network so as to balance out or compensate for differences in clock signal delay experienced at different portions of the PLD. As a result, the early PLL clock signal is received at substantially the same phase by all six clock selection circuits.
While earlier clock signal distribution networks in PLDs generally have been acceptable, there have been problems with their use. For example, there may be situations in which a PLD is programmed so that registers that temporarily store logic signals are separated by long line delays or by delays due to combinatorial logic. More specifically, in a PLD programmed for synchronous operation, the total register-to-register delay is approximately the sum of register clock-to-output time plus line delay between registers plus register setup time. The PLD clock generally cannot be run faster than the register-to-register delay. Thus, when logic signals in a PLD must be conducted along relatively long paths between registers or along paths between registers that are delayed by combinatorial logic, then the register-to-register delay may have a significant impact on device performance.
Thus, there exists a need for a programmable logic device with a clock signal network that can more effectively manage register-to-register delays experienced by logic signals. The present invention meets this need.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides an integrated circuit programmable logic device with a plurality of programmable logic elements that are responsive to clock signals. A clock signal generation circuit produces a first clock signal. A first phase shifting element produces a second clock signal which is a phase-shifted version of the first clock signal, shifted in phase by an amount which compensates for a logic signal delay. A clock signal distribution network distributes the first and second clock signals among the programmable logic elements.
In another aspect, the present invention provides a method of propagating logic signals in an integrated circuit programmable logic device which comprises a plurality of programmable logic elements. The programmable logic elements are programmed such that a logic output of

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