Register transfer level (RTL) based scan insertion for...

Details Register transfer level (RTL) based scan insertion for... Register transfer level (RTL) based scan insertion for...

1997-10-17

2001-07-03

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06256770

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the design of integrated circuits and other complex electonic circuits, and more particularly to circuit design processes which make use of automated computer-implemented design techniques.
BACKGROUND OF THE INVENTION
Application-specific integrated circuits (ASICs) and other types of complex electronic circuits are often designed using Register Transfer Level (RTL) techniques. In an RTL-based design process, the design is initially expressed in a high level computer language such as VHSIC (very High Speed Integrated Circuit) Hardware Description language (VHDL), which is a standard of the Institute of Electrical and Electronics Engineers (IEEE). The design as expressed in the high level language is then converted to a gate-level description using a process referred to as synthesis. The synthesis process optimizes the gate-level description within the area and timing constraints of the particular design. The complexity of the synthesis process typically requires that a large ASIC design be partitioned into several modules which are then synthesized separately, often by different designers. Before entering the synthesis process, the modules are simulated in RTL VHDL format using functional vectors to verify the desired functionality of the module. This simulation is also performed on the complete set of RTL VHDL code for the design.
ASICs and other complex circuits may also make use of Design for Test (DFT) techniques which modify the design to ensure that the final gate-level design is testable for internal faults such as “stuck-at-one” or “stuck-at-zero” conditions on signal lines, A gate-level design is generally considered testable if it is possible to obtain a sufficiently high fault coverage by using test vectors generated by an automatic test pattern generator program or by on-chip logic configured to provide a function referred to as Built-In Self Test (BIST). BIST eliminates the need for test generation and allows at-speed testing by embedding test generation and signature computation hardware within the design. For example, a scan-based BIST technique involves connecting a series of flip-flops in the gate-level design into a scan chain. A control signal may then be set to a particular value in order to place the circuit into a scan mode, such that logic values can be shifted from one flip-flop to the next with every clock cycle, his allows testing of combinational logic between the flip-flops which would otherwise be very difficult to observe and control to a specific value during test.
Conventional scan chains for BIST are often constructed by modifying the flip-flops in the gate-level design. A scan chain implemented in this manner generally results in an extra multiplexor delay for signals passing through the corresponding flip-flops, as well as additional loading on the flip-flop outputs. In RTL-based design applications, this implementation of conventional scan chains can lead to new violations of the timing and area constraints, thus requiring that a computationally-intensive and costly re-optimization phase be performed on the entire design at the end of the design process. Implementing scan-based BIST using conventional techniques thus unduly increases the cost and complexity of the overall design process.
A number of approaches have attempted to implement DFT functions at the RTL VHDL level of a design. These approaches are described in, for example, S. Bhattacharya and S. Dey, “H-SCAN: A High Level Alternative to Full-Scan Testing with Reduced Area and Test Application Overheads,” 14
th
VLSI Test Symposium, IEEE, pp. 74-80, 1996; R. S. Norwood and E. J. McCluskey, “Synthesis-for-Scan and Scan Chain Ordering,” 14
th
VLSI Test Symposium, IEEE, pp. 87-92, 1996; K. D. Wagner and S. Dey, “High-Level Synthesis for Testability: A Survey and Perspective,” Proceedings of Design Automation Conference, pp. 131-136, 1996; and C. Papachristou and J. Carletta, “Test Synthesis in the Behavioral Domain,” Proceedings of the International Test Conference, IEEE, pp. 693-702, 1995, all of which are incorporated by reference herein. However, each of these approaches has one or more significant drawbacks. For example, some of these approaches fail to provide scan chains which can be used for applying diagnostic or supplementary deterministic vectors, while at least one other fails to provide scan-based BIST functions suitable for use in a wide variety of designs.
SUMMARY OF THE INVENTION
The invention provides techniques for modifying Register Transfer Level (RTL) or other design-level circuit descriptions such that after synthesis the resulting gate-level description includes scan chains that can be used for Built-In Self Test (BIST) or other types of scan testing. In an illustrative embodiment, a complete RTL VHDL description of a circuit is modified to incorporate testability functions in the form of scan chains. The RTL VHDL description includes processes describing operations of the circuit. The processes for the complete circuit description are first analyzed to identify data carriers such as signals or variables which correspond to flip-flops or other specified elements in the circuit. This analysis may involve locating certain types of process structures, such as clocking statements, which are generally associated with the specified elements. The specified elements are organized into scan chains, and different portions of the scan chains are allocated to different modules of the circuit by associating each signal or variable with the module that generates it. These chain selection and allocation operations are performed on the complete RTL VHDL description of the circuit.
After the chain selection and allocation, each of the modules in the RTL VHDL description of the circuit is subject to separate scan ordering, scan insertion and synthesis operations. The scan ordering operation for a given module is based on functional relationships, including both word-level and bit-level dependencies, between the signals or variables in the processes associated with the given module. The scan ordering may analyze the functional relationships between data carriers using a signal-variable graph which includes edges of the form (n
1
, n
2
) where n
1
and n
2
are signals or variables in a process. Priorities assigned to edges of the signal-variable graph are used to order scan chains having desired chain lengths. The scan insertion operation for a given module involves inserting scan assignment statements into the processes associated with the given module. The modified RTL VHDL descriptions of the modules are then separately synthesized to generate gate-level descriptions of the modules, such that the resulting gate-level description of the circuit includes the appropriate scan chains.
The invention, by making use of word-level dependencies, bit-level dependencies and other functional relationships identifiable in the RTL source code, is able to order the scan chains in a manner which substantially reduces the area overhead of the synthesized design. Moreover, inserting scan chains at the RTL source code level in accordance with the invention allows a designer to utilize the full power of a synthesis process to optimize both the test and functional logic circuitry. This is particularly useful in BIST applications, since the test logic usually needs to operate at the same speed as the functional logic. Because the invention allows test logic and functional logic to be optimized together, the final design is better optimized than it would be in a conventional approach using, for example, gate-level scan insertion followed by a re-optimization phase. The invention can be integrated with an iterative synthesis process, using simple and readily identifiable modifications to VIDL source code, and with substantially no loss of fault coverage as evaluated at the gate level relative to conventional gate-level scan insertion.


REFERENCES:
patent: 5748497 (1998-05-01), Scott et al.
patent: 5812561 (1998-09-01), Giles et al.
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