Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-10
2001-07-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000
Reexamination Certificate
active
06261954
ABSTRACT:
BACKGROUND OF THE INVENTION
(1). Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of depositing a copper layer in the manufacture of integrated circuit devices.
(2). Description of the Prior Art
Several approaches are currently available for depositing copper in integrated circuit manufacturing. First, the copper may be deposited by physical vapor deposition (PVD). PVD, or ionized PVD, processes benefit from available technology and relatively high throughput. However, PVD deposited copper has poor step coverage. Second, chemical vapor deposition (CVD) offers better step coverage than PVD. However, CVD is not yet a mature process and is expensive to use.
Third, electroplating and electroless plating of copper are attractive alternatives to PVD and CVD because of lower equipment and material costs. However, plating methods require the presence of a seed layer to conduct or to catalyze the deposition reaction. This seed layer typically comprises copper, though other materials such as refractory metals have been suggested. When this seed layer is copper, it is typically deposited by a PVD process. In addition, electroless plating may require an induction layer as a catalytic surface. Alternatively, copper may be plated by the reduction of Cu
2+
by a reducing agent such as aldehyde and hypophosphite. Finally, plating processes can be very slow and dirty.
The purpose of the present invention is to achieve a new method for depositing a copper layer in the manufacture of an integrated circuit device. The new method is simpler, cleaner, and cheaper than the existing methods.
Several prior art approaches disclose methods to deposit copper layers in an integrated circuit device and related topics. In I. V. Nelson et al, “Polarographic Evidence for the Stability of Copper (I) Ion in some Non-Complexing Non-Aqueous Solvents,”
The Journal of Inorganic Nuclear Chemistry
, Volume 22, 1961, pp. 279-284, the stability of the cuprous ion (Cu+or Cu(I)) is studied. Cu(I) ion appears more stable in solvents such as methanol, ethanol, 1-propanol, 2-propanol, allyl alcohol, acetone, mesityl oxide, acetylacetone, acetic anhydride, nitromethane, and pyridine. This stability is actually due to lower salvation energy of cupric (Cu
2+
or Cu(II)) ion in these solvents and not due to higher salvation energy of Cu(I). U.S. Pat. No. 5,354,712 to Ho et al discloses a method to deposit copper for integrated circuit metalization. The copper layer is deposited by an organo-metallic chemical vapor deposition (OM-CVD) on a seed layer of titanium nitride. U.S. Pat. No. 5,376,248 to Conrod et al teaches an electrolytic process for plating a conductive material onto a plastic circuit board. A copper plating processing example is given where an aqueous solution of Cu
2+
is disproportionated to plate copper. U.S. Pat. No. 5,674,787 to Zhao et al teaches a method to selectively deposit copper by electroless plating. A titanium nitride barrier layer is formed. A silicon nitride layer is deposited on the sidewalls of the dual damascene trenches. Copper atoms are electroless plated overlying the titanium nitride barrier layer by a conventional plating solution. A copper layer is then electroless plated to fill the trench and the damascene device is completed. U.S. patent application Ser. No. 09/501,966 (CS-99-158) to H. K. K. Paul et al teaches a method of reacting CuF
2
vapor with a barrier layer to form a thin and conformal Cu seed layer.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of depositing a copper layer in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to deposit a copper layer using disproportionation of simple Cu(I) ions from a solution stabilized by a polar organic solvent.
A yet further object of the present invention is to provide a method to deposit a copper seed layer, using disproportionation of simple Cu(I) ions from a solution stabilized by a polar organic solvent, for use in subsequent electroplating and electroless copper plating of single and dual damascene interconnects.
Another further object of the present invention is to provide a method to deposit a copper layer, using disproportionation of simple Cu(I) ions from a solution stabilized by a polar organic solvent, for single and dual damascene interconnects.
In accordance with the objects of this invention, a new method of depositing a copper layer, using disproportionation of simple Cu(I) ions from a solution stabilized by a polar organic solvent, for forming single and dual damascene interconnects in the manufacture of an integrated circuit. device has been achieved. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer is patterned to form vias and trenches for planned damascene interconnects. The damascene interconnects may be either single or dual damascene. A barrier layer is deposited overlying the dielectric layer to line the vias and trenches. A simple Cu(I) ion aqueous solution, stabilized by a polar organic solvent, is coated overlying the barrier layer. Water is added to the stabilized Cu(I) ion solution to induce disproportionation of the Cu(I) ion from the Cu(I) ion solution. Optionally, the polar organic solvent is evaporated from the stabilized Cu(I) ion aqueous solution to induce disproportionation of the Cu(I) ion from the Cu(I) ion solution. A copper layer is deposited overlying the barrier layer. The copper layer may comprise a thin seed layer for use in subsequent electroplating or electroless plating or may comprise a thick copper layer to fill the vias and trenches. The integrated circuit is completed.
REFERENCES:
patent: 5354712 (1994-10-01), Ho et al.
patent: 5376248 (1994-12-01), Conrod et al.
patent: 5654245 (1997-08-01), Allen
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5918150 (1999-06-01), Nguyen et al.
I. V. Nelson etal. , J. Inorg. Nucl. Chem.. 1961, vol. 22. pp 279-284, Polarrographic Evidence For The Stability Of Copper (I) lohn In Some Non-Complexing Nonaqueus Solvents.*
I.V. Nelson et al., “Polarographic Evidence for the Stability of Copper (I) Ionin some Non-Complexing Non-Aqueous Solvents”, The Journal of Inorganic Nuclear Chemistry, vol. 22, 1961, pp. 279-284.
Chooi Simon
Gupta Subhash
Ho Paul Kwok Keung
Zhou Mei Sheng
Chartered Semiconductor Manufacturing Ltd.
Le Dung A
Nelms David
Pike Rosemary L. S.
Saile George O.
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