Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
1997-10-31
2001-05-08
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C712S229000
Reexamination Certificate
active
06230259
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to microprocessors, and more particularly to a method and apparatus for saving an extended state of a microprocessor.
2. Description of the Relevant Art
Microprocessor manufacturers continue to develop new products which execute X86 instructions in order to maintain compatibility with the vast amount of software developed for previous X86 processor generations—the 8086/8, 80286, 80386, and 80486. Maintaining software compatibility has forced many architectural compromises in newer products. In order to retain the functions of earlier products, hardware has often been simply modified or extended in order to increase capability and performance.
The X86 instruction set (hereinafter also referred to as the standard instruction set) is relatively complex and is characterized by a plurality of variable byte length instructions. The instructions, when executed by a microprocessor, can access X86 standard or general purpose(e.g., EAX, EBX, ECX, EDX, EBP, ESI, EDI ESP) registers. A generic format illustrative of the X86 instruction set is shown in FIG.
1
. As illustrated in the figure, an X86 instruction consists of from one to five optional prefix bytes
102
, followed by an operation code (opcode) field
104
, an optional addressing mode (Mod R/M) byte
106
, an optional scale-index-base (SIB) byte
108
, an optional displacement field
110
, and an optional immediate data field
112
.
The opcode field
104
defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more prefix bytes. For example, a prefix byte may be used to change the address or operand size for an instruction, to override the default segment used in memory addressing, or to instruct the processor to repeat a operation string a number of times. The opcode field
104
follows the prefix bytes
102
, if any, and may be one or two bytes in length. The addressing mode (Mod R/M) byte
106
specifies the registers used as well as memory addressing modes. The scale-index-base (SIB) byte
108
is used only in 32-bit base-relative addressing using scale and index factors. A base field of the SIB byte specifies which register contains the base value for the address calculation and an index field specifies which register contains the index value. A scale field specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is the optional displacement field
110
, which may be from one to four bytes in length. The displacement field
110
contains a constant used in address calculations. The optional immediate field
112
, which may also be from one to four bytes in length, contains a constant used as an instruction operand. The shortest X86 instructions are only one byte long, and comprise a single opcode byte. The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386 and 80486 both allow instruction lengths of up to 15 bytes.
FIGS. 2 and 3
illustrate the internal fields associated with the Mod R/M byte and of the SIB byte, respectively. References to a register of the X86 architecture may appear within the REG/OP or the R/M field of the Mod R/M byte, or within the index field and base field of the SIB byte. (A register address may alternatively be implied by an opcode.) Thus, there are four possible references to a register in an X86 instruction (although only three register references may appear in any particular instruction). The REG/OP and R/M fields in the Mod R/M byte can specify the source and destination registers, and the base and index fields in the SIB byte can specify the base and index registers used in operand address calculations for memory accesses.
A significant deficiency of the X86 architecture is the small number of standard registers. Typical RISC processors have at least thirty-two standard registers, as opposed to eight for the X86. A larger standard register set allows more operands to be stored in the faster-access register file, rather than in relatively slow memory. Modern compilers are also able to take advantage of a larger number of registers to expose greater instruction level parallelism for increased superscalar execution performance. In addition to the limited number of standard X86 registers, use of them by the compiler is complicated by the fact that most have special implicit uses in various instructions. Extending the number of standard registers would alleviate these limitations. However, extending the number of standard registers creates problems with saving the state of a suspended process employing the extended register set. Normally, when a microprocessor suspends one process to begin a new process, the operating system is intensely involved with saving the state of the suspended process until it is restarted. Generally, the state of the suspended process, including the contents of the standard at the registers point of suspension, is saved in main memory until it is recalled for further processing.
The operating system is configured to save the state of X86 processes, i.e., processes employing the standard X86 registers. Unless the operating system is reconfigured, the operating system may not be able to save the state of processes employing the extended register set. Reconfiguring the operating system to take advantage of applications of microprocessor extensions can be expensive and time consuming.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a microprocessor having a standard register set and an extended register set, which can save the state of a process employing the extended register set without requiring a modification of existing operating system configured to save the state of a process employing the standard register set.
The microprocessor of the present invention includes a core which is configured to execute both standard register processes and extended register processes. A first memory is provided for storing standard register process states when a standard register process executing on the microprocessor core is suspended. A second memory is provided for storing extended register process states when an extended register process executing on the microprocessor core is suspended. An extended state save circuit coupled between the microprocessor core and second memory saves the extended state of the microprocessor core in the second memory upon extended register process suspension.
The extended state save circuit saves the microprocessor state into the second memory when the microprocessor core receives an instruction to suspend execution of an extended register process. The second memory is configured as a plurality of buffers several of which may be allocated to currently running (i.e., active) extended processes or to suspended extended register processes. Several of the buffers may not be allocated to extended processes. A memory array having a plurality of entries is also provided, each entry corresponding to one of the buffers within the second memory. Each entry within the memory array contains information indicating whether its corresponding buffer is allocated. Before a new extended register process executes, the extended state save circuit accesses the memory array to identify a buffer which has not been allocated. When a unallocated or free buffer is identified, it is allocated by the extended state save circuit to the new extended register process.
A memory buffer identification register is also provided for storing a memory buffer identifier identifing a memory buffer in which an extended register process is saved upon suspension thereof Thus, when an extended process is suspended, the extended state save circuit saves the state of the microprocessor core including the contents of the extended register set into the buffer identified by the buffer identification register. The identifier within the buffer identification register is saved so that in
Christie David S.
Kranich Uwe
Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Kowert Robert C.
Niebling John F.
Whitmore Stacy
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