Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-09-07
2001-10-16
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S205000, C365S227000
Reexamination Certificate
active
06304494
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to potential control of a dynamic random access memory.
2. Description of the Background Art
A personal computer and a workstation each include a memory for storing data. An example of the memory is a DRAM (Dynamic Random Access Memory) with a great capacity from and into which data can be read and written. The DRAM is used as a main memory in the personal computer, workstation and the like. In recent years, an embedded DRAM composed of a DRAM and a logic circuit such as arithmetic circuit which are mounted on the same chip has been employed in a digital still camera and a notebook personal computer.
A memory cell of the DRAM is constituted of one transistor and one capacitor. One memory cell stores 1 bit of information depending on whether or not charges are stored in the capacitor. Generally the supply voltage is reduced in order to decrease power consumption of the DRAM. However, just the reduction of the supply voltage results in decrease of the amount of charges stored in the memory cell. In order to avoid this decrease, capacitance of the capacitor may be increased. Increase of the capacitance is achieved by forming the capacitor as a stacked type having a three-dimensional structure so as to increase the area of the capacitor electrode, or forming a dielectric film of the capacitor of material having a high dielectric constant (high dielectric material) so as to increase relative dielectric constant.
The techniques of forming the capacitor having the three-dimensional structure or forming the dielectric film of high dielectric material both have been employed. However, in order to further decrease the power consumption by reducing the voltage, a capacitor of a more complicated three-dimensional structure or material with higher dielectric constant is requested. This complicates the manufacturing process, resulting in increased manufacturing cost.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device with decreased power consumption.
A semiconductor device according to one aspect of the present invention includes a pair of bit lines, first and second source lines, a sense amplifier, and a source potential control circuit.
A plurality of memory cells are connected to the pair of bit lines. The sense amplifier connected to the pair of bit lines and the first and second source lines amplifies potential on one of the bit lines to potential on the first source line and amplifies potential on the other bit line to potential on the second source line. When a write operation is requested, the source potential control circuit supplies a first potential to the first source line, supplies a second potential lower than the first potential to the second source line, and supplies a third potential higher than the first potential to the first source line after supply of write data to the pair of bit lines.
According to another aspect of the invention, a semiconductor device includes first and second pairs of bit lines, an N channel sense amplifier, a first pair of N channel MOS transistors, a second pair of N channel MOS transistors, first and second P channel sense amplifiers, a source potential control circuit, and a row decoder.
A plurality of memory cells are connected to each of the first and second pairs of bit lines. The N channel sense amplifier is shared by the first and second pairs of bit lines. The first pair of N channel MOS transistors is connected between the N channel sense amplifier and the first pair of bit lines. The second pair of N channel MOS transistors is connected between the N channel sense amplifier and the second pair of bit lines.
The first and second P channel sense amplifiers are connected respectively to the first and second pairs of bit lines. Each of the P channel sense amplifiers is connected to a source line and amplifies potential on one of the bit lines of the bit line pair connected thereto to potential on that source line.
When a write operation is requested, the source potential control circuit supplies a first potential to the source line, and supplies a second potential higher than the first potential to the source line after supply of write data to one of the first and second pairs of bit lines. The row decoder supplies a predetermined potential which is equal to or less than a second potential to the gates of the first and second pairs of N channel MOS transistors.
According to still another aspect of the invention, a semiconductor device includes first and second banks.
The first bank includes a first pair of bit lines to which a plurality of memory cells are connected, first and second source lines, and a first sense amplifier connected to the first pair of bit lines and the first and second source lines to amplify potential on one bit line of the first bit line pair to potential on the first source line and amplify potential on the other bit line thereof to potential on the second source line. The first bank further includes a first source potential control circuit which supplies, when a write operation is requested, a first potential to the first source line, supplies a second potential lower than the first potential to the second source line, and supplies a third potential higher than the first potential to the first source line after supply of write data to the bit line pair.
The second bank includes a second pair of bit lines to which a plurality of memory cells are connected, third and fourth source lines, and a second sense amplifier connected to the second pair of bit lines and the third and fourth source lines to amplify potential on one bit line of the second bit line pair to potential on the third source line and amplify potential on the other bit line thereof to potential on the fourth source line. The second bank further includes a second source potential control circuit which supplies, when a write operation is requested, the first potential and the second potential respectively to the third and fourth source lines, supplies the second potential to the fourth source line, and supplies the third potential to the third source line after supply of write data to the second pair of bit lines.
The write operation carried out in the second bank overlaps the write operation in the first bank.
A chief advantage of the present invention is accordingly that power consumption can be reduced by lowering the potential on the source line when the write operation is performed.
Another advantage of the invention is that gate potential of transistors for isolation gate provided between the bit lines and the N channel sense amplifier can be decreased and thus reduction of power consumption is possible.
Still another advantage of the invention is that decrease of speed due to lowered potential on the source line in the write operation can be avoided by bank operation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5229964 (1993-07-01), Yamauchi
patent: 5264058 (1993-11-01), Yamauchi
patent: 5719814 (1998-02-01), Ishikawa
patent: 5764580 (1998-06-01), Suzuki et al.
patent: 6088275 (2000-07-01), Tanaka
patent: 6115284 (2000-09-01), Matsumiya et al.
patent: 11-86549 (1999-03-01), None
patent: WO 9724729 (1997-07-01), None
patent: WO 97/28532 (1997-08-01), None
European Search Report dated Dec. 18, 2000.
Mai Son
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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