Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-12-01
2001-05-29
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C702S120000, C703S016000, C324S750010, C324S763010, C324S765010
Reexamination Certificate
active
06240543
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to computer-aided design tools and techniques for design, implementation, and simulation of complex circuits and systems particularly digital devices, modules and systems.
BACKGROUND OF THE INVENTION
Process Technology density in 1998 is 8 million gates and increasing at 60% more each year. Design productivity is at about 1 million gates and increasing at 20% each year. The gap between the two is widening. New capabilities are needed to dramatically improve design productivity.
Many existing integrated circuits can be integrated into very large integrated circuits (SOC or Systems on a Chip) to use the available silicon densities. The key is to have a productivity improvement in the migration of the existing integrated circuits in to SOC.
Present day state-of-the art design technique, uses simulation models of the Integrated Circuits, translates these models to various levels down to the level where silicon can be manufactured. The levels are RTL (Register Transfer Level), gate, or transistor. Simulation is inadequately slow at 300,000 gates, and intolerable at 1 million gates.
Many existing integrated circuits do not have accurate RTL models. If the RTL models do exist, it is a long path to fully integrated silicon, as synthesis needs to be redone, test needs to be redone. Manufacturing test is key to success of SOC.
The traditional methods are slow and arduous for SOC, provide little leverage of existing integrated circuit design, and do not provide for a non-functional simulation flow.
BRIEF SUMMARY OF THE INVENTION
This invention is a system and method for developing SOC rapidly, leveraging existing integrated circuits, promoting the greatest benefits of Intellectual Property integration and re-use with the shortest design cycle.
There are three key steps in the flow. The first step is developing the test model for the SOC. The second step is taking the refined test model to layout and doing the physical design migration of the chips to cores using existing re-layout tools. The third step prepares the SOC for fabrication, fabrication is done, and the SOC is used in a target board. This enables a full SOC development sourced from existing chips, done without functional simulation.
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Kik Phallaka
Smith Matthew
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