Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-04
2001-10-02
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S298000, C257S300000, C257S301000, C257S308000, C438S238000, C438S239000, C438S242000, C438S386000, C438S399000
Reexamination Certificate
active
06297524
ABSTRACT:
RELATED APPLICATIONS
Commonly-assigned, copending U.S. patent application, Ser. No. 09/545,785, entitled “Interdigitated Multilayer Capacitor Structure For Deep Sub-Micron CMOS”,filed Apr. 7, 2000.
Commonly-assigned, copending U.S. patent application Ser. No. 09/542,711, entitled “Combined Transistor-Capacitor structure In Deep Sub-Micron CMOS For Power Amplifiers”, filed Apr. 4, 2000.
Commonly-assigned, copending U.S. patent application, Ser. No. 09/596,443, entitled “Multilayer Pillar Array Capacitor Structure For Deep Sub-Micron CMOS”, filed Jun. 19, 2000.
Commonly-assigned, copending U.S. patent application Ser. No. 09/546,125, entitled “Multilayered Capacitor Structure With Alternately Connected Concentric Lines For Deep Sub-Micron CMOS”, filed Apr. 10, 2000.
FIELD OF THE INVENTION
This invention relates to capacitor structures for metal-oxide-semiconductors (MOS), and in particular, to a capacitor structure for deep sub-micron complementary metal-oxide semiconductors (CMOS), formed by multiple levels of electrically conductive ring-shaped concentric lines connected between levels by vias that define an array of concentric ring-shaped capacitor plates.
BACKGROUND OF THE INVENTION
Conventional capacitor structures for deep sub-micron CMOS are typically constructed with two flat parallel plates separated by a thin dielectric layer. The plates are formed by layers of conductive material, such as metal or polysilicon. The capacitor structure is usually isolated from the substrate by an underlying dielectric layer. To achieve high capacitance density in these structures, additional plates are provided.
FIG. 1
illustrates a conventional multilayer parallel plate capacitor structure
10
in a deep sub-micron CMOS. The capacitor structure
10
includes a vertical stack of electrically conductive lines
12
separated by dielectric layers
13
. The conductive lines
12
and dielectric layers
13
are constructed over a semiconductor substrate
11
. The conductive lines
12
form the plates or electrodes of the capacitor
10
. The plates
12
are electrically connected together in an alternating manner such that all the “A” plates are of a first polarity and all the “B” plates are of a second polarity, opposite to the first polarity.
A major limitation associated with parallel plate capacitor structures is that the minimum distance between the plates does not change as geometries in CMOS processes are scaled down. Hence, gains in capacitance density are not realized during such down scaling.
Various other capacitor structures with high capacitance densities, such as double polysilicon capacitors and gate-oxide capacitors, are known in the art. Double polysilicon capacitors, however, do not lend themselves to deep sub-micron CMOS processes. Gate-oxide capacitors are generally not used in deep sub-micron CMOS processes because they have large gate areas which cause yield and reliability issues, they generate capacitances which vary with voltage, and may experience high voltages that can breakdown the gate-oxide.
Trench capacitor structures for dynamic random access memories (DRAMs) have high capacitance densities. Such capacitors are formed by etching a trench in the substrate and filling the trench with conductive and dielectric material to form a vertical capacitance structure. However, trench capacitors are costly to fabricated because they add etching and trench filling processes.
Interdigitated capacitor structures are used in microwave applications. These capacitors have closely placed, interdigitated conductive line structures which produce fringing and crossover capacitances therebetween to achieve capacitance. However, the cross-over capacitance produced by interdigitated capacitors is limited to a single conductor level.
Accordingly, a need exists for an improved high capacitance density capacitor structure for deep sub-micron CMOS.
SUMMARY OF THE INVENTION
A capacitor structure comprising a first and at least a second conductor level of electrically conductive concentric lines. The conductive lines of the first and at least second levels are arranged in concentric stacks. A dielectric material is disposed between the first and second conductor levels and between the concentric conductive lines in each of the levels. At least one electrically conductive via electrically connects the conductive lines in each stack, thereby forming a concentric array of capacitor plates. The concentric array of capacitor plates are electrically connected in an alternating manner to first and second terminals of opposite polarity so that capacitance is generated between adjacent plates of the array. The capacitor structure is especially useful in deep sub-micron CMOS.
REFERENCES:
patent: 5583359 (1996-12-01), Ng et al.
patent: 5753949 (1998-05-01), Honma et al.
patent: 11-312855 A (1999-11-01), None
Sowlati Tirdad
Vathulya Vickram
Flynn Nathan
Philips Electronics North America Corporation
Quinto Kevin
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