Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-08
2001-04-17
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S648000, C438S672000, C438S740000
Reexamination Certificate
active
06218287
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the deposition of metal on a semiconductor structure, and more specifically to a method of fabricating a semiconductor structure in which metal is deposited to from an improved via connection despite misalignment between via hole and trench pattern.
2. Description of the Related Art
U.S. Pat. No. 4,789,648 issued to M. M Chow et al discloses a method of depositing metal on a semiconductor structure. According to this prior art, a layered structure of insulating material is provided on a semiconductor substrate in which a layer of metallization is formed. The layered insulator structure consists of a etch stop layer sandwiched between lower and upper insulating layers. The etch stop layer has a window. A photoresist layer having a trench pattern is then deposited on the structure and the portion of the upper insulating layer is etched through the trench pattern to form a wire trench. The etching process is continued to etch the portion of the lower insulating layer through the window of the etch stop layer down to the layer of metallization to form a via hole. Metal is then deposited into the via hole and the wire trench to complete a via connection between the metallization and the conductor in the wire trench.
However, if the trench pattern is misaligned with the window of the etch stop layer, the effective contact area of the metal in the via hole and the metal in the wire trench is reduced. Such a reduced contact area is a potential source of failures.
Further, the etch stop layer is exposed to etching gas while the etching process is continued to form the via hole. Therefore, the etch stop layer must be of a material capable of withstanding erosion under the etching gas, and hence the material that forms the wire trench has a high dielectric constant. As a result, the parasitic capacitance between adjacent wire conductors increases to the detriment of high speed performance of semiconductor devices.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of fabricating a semiconductor structure which ensures a via connection with no reduced contact area, despite misalignment.
A further object of the present invention is to provide a method of fabricating a semiconductor structure which ensures low dielectric constant for wire conductors in order to achieve high speed operation of the semiconductor device.
According to a first aspect of the present invention, there is provided a method of fabricating a semiconductor structure, comprising the steps of providing a substrate having a doped region, forming a successively layered structure on the substrate, the layered structure comprising a lower insulating layer, a lower etch stop layer, an upper insulating layer and an upper etch stop layer, forming a via hole above the doped region, the via hole extending through the upper etch stop layer and the upper insulating layer to the lower etch stop layer, forming, on the upper etch stop layer, a photoresist layer having a trench pattern, forming a replica of the trench pattern on the upper etch stop layer, removing any of the photoresist layer, simultaneously removing a portion of the upper insulating layer through the replica of the trench pattern to form a wire trench and a portion of the lower insulating layer through the removed portion of the lower etch stop layer to extend the via hole to the doped region, simultaneously removing the upper etch stop layer and a portion of the lower etch stop layer through the wire trench, and depositing metal in the via hole and the wire trench.
According to a second aspect, the present invention provides a method of fabricating a semiconductor structure, comprising the steps of providing a substrate having a doped region, forming a successively layered structure on the substrate, the layered structure comprising a lower etch stop layer, a lower insulating layer, a middle etch stop layer, an upper insulating layer and an upper etch stop layer, forming a via hole above the doped region, the via hole extending through the upper etch stop layer, the upper insulating layer to the middle etch stop layer, forming, on the upper etch stop layer, a photoresist layer having a trench pattern, forming a replica of the trench pattern on the upper etch stop layer, removing any of the photoresist layer, simultaneously removing a portion of the upper insulating layer through the replica of the trench pattern to form a wire trench and removing a portion of the lower insulating layer through the removed portion of the middle etch stop layer to extend the via hole to the lower etch stop layer, simultaneously removing the upper etch stop layer, a portion of the middle etch stop layer through the wire trench and a portion of the lower etch stop layer through the via hole, and depositing metal in the via hole and the wire trench.
REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 5818110 (1998-10-01), Cronin
patent: 5976972 (1999-11-01), Inohara et al.
patent: 6025259 (2000-02-01), Yu et al.
patent: 6071806 (2000-06-01), Wu et al.
patent: 6071809 (2000-06-01), Zhao
patent: 6083822 (2000-07-01), Lee
patent: 6093632 (2000-07-01), Lin
patent: 6143646 (2000-11-01), Wetzel et al.
McGinn & Gibb PLLC
NEC Corporation
Quach T. N.
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