Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-03-09
2001-04-24
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S154000, C365S230060
Reexamination Certificate
active
06222780
ABSTRACT:
BACKGROUND LINE OF THE INVENTION
(a) Field of the Invention
The present invention relates to a high-speed SRAM (static random access memory) having a stable cell ratio and, more particularly, to an improvement of a SRAM having four-transistor memory cells in the operational speed and a data hold characteristic.
(b) Description of a Related Art
SRAMs have been used in the field where a high-speed operation is desired. SRAMs having four-transistor memory cells of a CMOS structure are used more or more due to its capability of higher-density integration and more stable operation compared to the conventional SRAM.
Patent Publication JP-A-6-104405 describes a SRAM having four-transistor memory cells of a CMOS structure, such as shown in FIG.
1
. The memory cell includes a pair of transfer pMOS transistors
11
and
12
, and a pair of driver nMOS transistors
13
and
14
. An internal node P
1
is connected through transfer pMOS transistor
11
to a digit line
15
, through driver nMOS transistor
13
to the ground line, and directly to the gate of driver nMOS transistor
14
. Another internal node P
2
is connected through driver pMOS transistor
12
to another digit line
16
, through driver nMOS transistor
14
to the ground line, and directly to the gate of driver nMOS transistor
13
. The gates of pMOS transistors
11
and
12
are connected to a word line
17
.
In a write operation, the potential of the word line
17
is lowered to a low level for turning on transfer pMOS transistors
11
and
12
, and one of driver MOSFETs
13
and
14
is turned on and the other is turned off by a potential difference between digit lines
15
and
16
.
In a read operation, the potential of the word line
17
is also lowered to a low level to cause the potential difference between digit lines
15
and
16
due to the potentials of internal nodes P
1
and P
2
, which depend on the on- or off-state of driver nMOS transistors
13
and
14
.
In a data-hold operation, the word line
17
is maintained at a high level to turn off transfer pMOS transistors
11
and
12
, and digit lines
15
and
16
are applied with the VCC potential, whereby one of driver nMOS transistors
13
and
14
is turned on by the negative resistance of a corresponding driver nMOS transistor
13
or
14
passing a sub-threshold leak current.
In the conventional SRAM as described above, the pMOS structure of transfer transistors
11
and
12
allows one of the internal nodes P
1
and P
2
to assume a VCC potential level substantially without a voltage drop caused by the threshold voltage of the transistors after the Write operation. This in turn allows the memory cell to operate with a low voltage power source. In addition, since the transfer pMOS transistors acting as negative resistance elements in the data hold mode can be fabricated as TFTs above the driver nMOS transistors, a smaller occupied area can be obtained for the circuit pattern.
The conventional SRAM has the following problems however. First, it is difficult to select a suitable value for the cell ratio due to the un-uniformity of the resistance characteristics of MOSFETs which depend on the process conditions in the fabrication process thereof. The term “cell ratio” as used herein means the ratio of the off-resistance of the transfer pMOS transistors to the off-resistance of the driver nMOS transistors. The cell ratio determines the off-leak current of the transfer pMOS transistors which allows the driver nMOS transistors to hold the memory in a data hold mode, and also determines the on-current of the driver pMOS transistors so that the source-drain voltage drop of the driver pMOS transistor is equal to or below 0.3 volt in a read mode.
Second, during the write operation wherein the internal node P
1
or P
2
is lowered from the VCC level to the ground level by the digit lines
15
or
16
through the transfer pMOS transistors, the transfer pMOS transistors have a higher on-resistance in the vicinity of 1 volt for the gate voltage thereof, or around the threshold voltage. The higher on-resistance reduces the operational speed of the SRAM in the write operation.
Third, there is a large recovery time after the end of the write operation for the digit lines to prepare the start of the next read cycle by raising the potential of the digit lines up to the VCC level. In this situation, since the pMOSFET has lower current driveability compared to the nMOSFET, the dimensions of the pMOSFET should be increased in order to reduce the recovery time length. However, the larger dimensions of the pMOSFET with respect to the nMOSFET, that is, the smaller dimensions of nMOSFET with respect to the pMOSFET, results in a smaller occupied area for the memory cell, and thus reduces the distance between the digit lines, thereby raising the capacitance between the digit lines and impairing a high-speed operation of the SRAM.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a SRAM having a stable cell ratio and operating at a higher-speed by compensating the variations or un-uniformity of the cell ratio due to the process conditions in the fabrication process for the SRAM.
The present invention provides a SRAM including a plurality of memory cells arranged in a matrix and each including a pair of transfer transistors and a pair of driver transistors operatively connected for storing a cell data on a pair of internal nodes, a word line disposed for each row of the memory cells for driving gates of the transfer transistors of the memory cells in the each row, a pair of digit lines disposed for each column of the memory cells for transferring data through the transfer transistors of the memory cells in the each column, a word line driver disposed for each word line for activating the each word line, one of the driver nMOS transistors passing an off-leak current supplied from a corresponding one of the digit lines through a corresponding one of the transfer transistors in an off-state thereof to store the cell data, a precharge section for connecting the digit lines to a first source line for precharging, a write amplifier and a sense amplifier disposed for each column of the memory cells for storing/readifig data through the digit lines into/from the memory cells in the each column, and a reference voltage generator for generating a reference voltage which determines a cell ratio of each memory cell, the reference voltage having un-uniformity corresponding to un-uniformity of a potential of one of the internal nodes assuming a high level or low level.
In accordance with the SRAM of the present invention, a stable and optimum cell ratio can be obtained by the reference voltage, which cancels unstable hold operation caused by the un-uniformity of the cell ratio due to the process conditions by using un-uniformity of the reference voltage which determines the cell ratio.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 6-104405 (1994-04-01), None
Elms Richard
NEC Corpoartion
Nguyen Vanthu
Young & Thompson
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