Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-22
2001-10-02
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S336000, C257S345000, C257S408000, C257S486000, C257S740000, C257S900000, C438S286000
Reexamination Certificate
active
06297535
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacture of an integrated circuit and more particularly to the formation of an n-channel and/or p-channel transistor having barrier atoms incorporated in a lateral area under the drain-side of a gate dielectric to enhance transistor performance.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material and gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant material. If the impurity dopant material used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the source/drain dopant material is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device.
Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used. The methods by which n-channel devices and p-channel devices are formed entail unique problems associated with each device. As layout densities increase, the problems are exacerbated. N-channel devices are particularly sensitive to so-called short-channel effects (“SCE”). The distance between a source-side junction and a drain-side junction is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length (“Leff”). In VLSI designs, as the physical channel becomes small, so too must the Leff. SCE becomes a predominant problem whenever Leff drops below approximately 1.0 &mgr;m.
A problem related to SCE and the subthreshold currents associated therewith, but altogether different, is the problem of hot-carrier effects (“HCE”). HCE is a phenomena by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field (“Em”) occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. The electric field at the drain primarily causes electrons in the channel to gain kinetic energy and become “hot”.
As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor. It is known that since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in NMOS transistors than PMOS transistors. Nonetheless, a PMOS transistor will undergo negative threshold skew if its Leff is less than, e.g., 0.8 &mgr;m.
It is therefore desirable to develop a technique for fabricating transistors with reduced hot carrier injection into and trapping within the drain-side of a gate dielectric. Such a fabrication technique is necessary to prevent the accumulation of trapped charge within a gate dielectric, which would further help prevent the threshold voltage of a transistor from varying from its design specification. Since several types of semiconductor devices rely on the stability of transistor threshold voltage, uniformity of threshold voltage is desirable. The presence of a highly uniform and stable threshold voltage would provide for a highly reliable integrated circuit.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the improved method hereof for forming a p-channel or an n-channel transistor. That is, the present process involves incorporating barrier atoms into a lateral area underneath the drain-side of the gate oxide to abate HCE that result from hot carrier injection into the drain-side of the gate conductor.
So that barrier atoms may only be incorporated into the drain-side of the gate conductor, the drain-side spacer is removed while the source-side spacer is left behind to inhibit barrier atoms from migrating into an area underneath the source-side of the gate conductor. A sacrificial material may be formed between the gate conductor and the spacers on opposite sides of the gate conductor. The purpose of the sacrificial material is to allow the drain-side spacer to be selectively etched away without removing any portion of the gate oxide. Thus, the sacrificial material is preferably different in composition from the spacer material.
After the removal of the drain-side spacer, barrier atoms or ions may be compelled to traverse through the sacrificial material, i.e., “etch stop layer”, and into vacancies and opportune bond sites within and underneath a drain-side area of the gate oxide. The improvement in hot-carrier reliability is mainly attributed to the presence of barrier atoms at the interface between the silicon substrate and the gate oxide (i.e., the Si/SiO
2
interface), particularly in proximity to the drain. Thus, a majority of high-energy carriers (electrons or holes) cannot migrate into the gate oxide since barrier atoms occupy a substantial portion of the migration avenues at the substrate/oxide interface. Further, charge carrier trapping of electrons that escape into the gate oxide is limited because, e.g., strong Si—N bonds exist in place of weaker Si—H and strained Si—O bonds. Nitrogen atoms are preferably used as barrier atoms, however, it is not necessary the barrier atoms be limited exclusively to nitrogen.
Preferably, barrier atoms are strategically placed only in the critical area near the drain-side of the gate oxide. Barrier atoms thusly placed do not adversely affect the source-side of the transistor. It is postulated that barrier atoms unnecessarily positioned in vacancies within the channel may cause the output current, I
D
, of the transistor to undesirably decrease such that optimum device performance is unattainable. Output current may decrease because the barrier atoms occupy interstitial positions within the silicon crystal lattice, thereby deterring carrier mobility. In other words, the pathways that provide mobility for electrons and holes are blocked.
In an embodiment of the present invention, a gate oxide is thermally grown within and upon an upper surface of a silicon-based substrate. A layer of polysilicon is then deposited across the oxide layer. Portions of the oxide layer and the polysilicon layer may be removed to form a gate conductor interposed between an exposed pair of silicon substrate regions (henceforth referred to as source-side and drain-side junctions). The source-side and drain-side junctions are implanted with a dopant to form LDD areas therein. An etch stop material, such as a grown or deposited oxide may be formed upon opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the source-side and drain-side junctions.
Spacers may then be formed laterally adjacent the etch stop material located upon sidewall surfaces of the gate conductor. The spacers are made from a different material than the etch stop material. For instance, nitride spacers may be used. The combined lateral thickness of the space
Fulford Jr. H. Jim
Gardner Mark I.
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Lee Eddie
Warren Matthew E.
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