Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-10
2001-07-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S814000
Reexamination Certificate
active
06260176
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to making electrical circuits and more particularly to simulating phase lock loop circuits.
A phase lock loop is a feedback loop that forces a voltage controlled oscillator (VCO) to run in phase with a reference signal. For example, a frequency synthesizer application of a phase lock loop can generate a frequency that is a multiple of a reference frequency. Typically, a high frequency is generated from a low reference frequency. Phase lock loop circuits are used extensively in communication systems. They can be found, for example, in vertical hold and horizontal hold circuits and color controls in televisions
FIG. 1
is block diagram illustrating how a phase frequency detector
208
fits into a phase lock loop circuit
200
. Those skilled in the art will appreciate that there is a correspondence between the blocks in FIG.
1
and the function of physical circuit components and connections. As modeled in
FIG. 1
, a reference signal source
202
inputs a reference signal with reference frequency VREF into the phase lock loop circuit
200
. The reference signal source can be any of a panoply of sources including incoming data lines or radio signals having underlying carrier frequencies. The phase lock loop
200
locks onto the reference signal having frequency VREF.
A voltage controlled oscillator (VCO)
204
produces a signal having a VCO frequency. In some situations, it will be convenient to have a 1/N divider
206
in the phase lock loop
200
. The 1/N divider
206
divides a frequency of the VCO output by the number N. The divider
206
is particularly useful, for example, when the VCO
204
generates a high frequency carrier signal for a radio transmission, and the phase lock loop
200
checks the high frequency carrier against a low frequency VREF signal. The divider
206
produces a divided VCO signal with frequency VVCO which feeds back into a phase frequency detector
208
. In other implementations of the present invention, the 1/N divider
206
is absent, and the output of the voltage controlled oscillator
204
feeds directly into the phase frequency detector
208
. In many situations, the divider
206
can easily be modeled by a simple gain block.
The phase frequency detector
208
receives a reference frequency signal and a VCO frequency signal. The reference frequency variable is VREF. The outputs of the phase frequency detector
208
is essentially a loop filter input. The loop filter
210
strips the loop filter input of ripple and outputs the VCO input voltage to the VCO
204
.
The phase frequency detector
208
contains a digital state machine with states corresponding to loop filter inputs. The loop filter input is a charge pump having three states corresponding to a current source, a current sink, and current off. A state of the digital state machine is assigned one of the three states. The duty cycle refers to a relative time spent in a state of the digital state machine. This concept will be illustrated graphical by using a vector representation of the digital state machine.
In
FIG. 2A
, the current source state
212
is on top, and the current sink state
214
is on the bottom. The current off state
216
is between the current source state
212
and the current sink state
214
. The percentage of time spent in the top (or bottom) state is the duty cycle. The duty cycle is positive for top-middle toggling and negative for middle-bottom toggling. The duty cycle is “unlocked” when the phase lock loop
200
has not locked onto the reference frequency VREF.
In
FIG. 2B
, vector
218
represents a reference phase, and vector
220
represents a VCO phase. Both vectors
218
and
220
rotate counter-clockwise around an origin. Vector
218
rotates with frequency VREF, and vector
220
rotates with the frequency VVCO. An angle &thgr; between the vectors
218
and
220
equals phase error. The phase error is standardized to lie between +2 Pi and −2 Pi. Whenever the reference vector
218
passes a trigger line
222
, such as a vertical line, the state jumps to the next state up in FIG.
2
A. If the phase frequency detector
208
has output already in the (top) current source state
212
, it stays there. Whenever the VCO vector
220
passes the trigger line
222
, the state jumps to the next state down. If the phase frequency detector
208
output is already in the (bottom) current sink state
214
, it stays there.
If reference and VCO frequencies are essentially identical, the phase error is nearly constant as the vectors
218
and
220
rotate. For a fixed phase error, the state toggles between two states as the vectors
218
and
220
rotate. The state toggles between the (middle) current off state
216
and the (top) current source state
212
or between the (middle) current off state
216
and the (bottom) current sink state
214
.
Although the phase frequency detector
208
output current toggles between values, the loop filter
210
and VCO
204
respond to a percentage of time the digital state machine (phase frequency detector output) is in one of the two states, i.e. the duty cycle. At zero frequency error, the duty cycle equals phase error divided by 2*Pi. A transfer curve from phase error to duty cycle is resembles a multivalued sawtooth.
If reference and VCO frequency variables have a large difference, the average duty cycle becomes a monotonic function of a frequency ratio of the reference frequency and the VCO frequency. Suppose the reference frequency far exceeds the VCO frequency. Whenever the VCO vector
220
passes the trigger line
222
, the reference vector
218
passes shortly thereafter. The reference vector
218
may pass the trigger line
222
several more times before the VCO vector
220
passes the trigger line
222
again. The phase error still resembles a sawtooth waveform but an average duty cycle is nearly 1. Although this is an accurate statement of phase lock loop function, conventional phase models (described below) are unable to simulate on a computer average duty cycles close to 1.
Phase lock loops having phase frequency detectors
208
are traditionally very difficult to simulate. Important goals of a phase lock loop simulation are to determine how long a VCO
204
takes to lock onto the reference signal and what frequencies and phase the VCO
204
produces as it approaches the reference frequency. The VCO frequency is usually several orders of magnitude greater than the bandwidth of the loop. Consequently, to study loop dynamics a simulation may need to cover thousands to millions of oscillator periods.
Two kinds of conventional phase lock loop models exist: voltage and phase. Voltage models simulate each cycle of action. Consequently, simulated voltages correspond to voltages one could measure in a circuit. Voltage models have long run times but can simulate large-signal transients, i.e. deviations about a lock frequency as the phase lock loop
200
settles into the lock frequency. Voltage models are extremely slow because they must simulate every cycle of action. Therefore, they can easily take days to simulate the millions of cycles occurring in one transient as phase lock is approached. Conventionally, only voltage models can simulate large signal transients.
“Phase model” refers to modeling the voltage-controlled oscillator (VCO) as just an integrator. Phase models run hundreds to thousands of times faster than voltage models. Non-linear phase models exist but only for simple phase detectors such as XOR gates or analog multipliers. The phase model for an analog multiplier for example simply models input to the loop filter as the sine of phase error; the model has no memory (does not depend upon previous inputs), is single-valued, and is easily modeled with a single line in a behavioral source.
Conventional phase frequency detector models of phase lock loop circuits are either linear or conceptual. Linear models ignore important mode changes. Conceptual models are too difficult to implement with any simulator. The modeling complexity comes from
Do Thuan
Lyon & Lyon LLP
Smith Matthew
LandOfFree
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