Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-02-17
2001-05-15
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S190000, C365S225700
Reexamination Certificate
active
06233181
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device having a memory array divided into a plurality of memory blocks. More specifically, the present invention relates to a redundancy circuit for repairing a defective memory cell in a semiconductor memory device having such an array-divided arrangement and a power supply circuit provided corresponding to each block.
2. Description of the Background Art
In the semiconductor memory device, a defective memory cell is replaced with a spare memory cell in order to equivalently repair the defective memory cell to raise the yield of the products. A flexible redundancy scheme has been proposed in order to improve the use efficiencies of spare lines (word lines or bit lines) and spare decoders for selecting spare lines in a redundancy circuit configuration including spare memory cells (spare word lines and bit lines) for repairing such defective memory cells (see, for example, “A Flexible Redundancy Technique for High-Density DRAM's”, Horiguchi et al., IEEE Journal of Solid-State Circuits, Vol. 26, No. 1, January 1991, pp. 12 to 17).
FIG. 53
is a schematic diagram of the general configuration of a semiconductor memory device having a conventional flexible redundancy scheme. In
FIG. 53
, the semiconductor memory device includes four memory arrays MA
0
to MA
3
. In each of memory arrays MA
0
to MA
3
, a spare word line to repair a defective memory cell row is provided. In memory array MA
0
, spare word lines SW
00
and SW
01
are provided, and in memory array MA
1
, spare word lines SW
11
and SW
11
are provided. In memory array MA
2
, spare word line SW
20
and SW
21
are provided, and in memory array MA
3
, spare word lines SW
30
and SW
31
are provided.
Row decoders X
0
to X
3
each for decoding an address signal to drive a normal word line provided corresponding to an addressed row into a selected state are provided corresponding to memory arrays MA
0
to MA
3
. A column decoder Y
0
is provided between memory arrays MA
0
and MA
1
to decode a column address signal to select an addressed column, and also a column decoder Y
1
is provided between memory arrays MA
2
and MA
3
.
The semiconductor memory device further includes spare decoders SD
0
to SD
3
to store a row address at which a defective memory cell is present, maintain a word line (defective normal word line) corresponding to this defective row address in a non-selected state when the defective row is addressed and drive a corresponding spare word line into a selected state, an OR circuit G
0
to receive output signals from spare decoders SD
0
and SD
1
, and an OR circuit G
1
to receive output signals from spare decoders SD
2
and SD
3
.
The output signals of OR circuits G
0
and G
1
are provided in common to spare word line driving circuits included in row decoders X
0
to X
3
. Spare decoders SD
0
to SD
3
are commonly provided with array address signal bits an-
2
and an-
1
to address one of memory arrays MA
0
to MA
3
and with intra-array address signals bits a
0
to an-
3
to address a row in the memory array. Row decoders X
0
to X
3
are provided with array address signal bits an-
2
and an-
1
, and a row decoder is activated when a corresponding memory array is addressed. OR circuits G
0
and G
1
each correspond to two spare word lines provided for each of memory arrays MA
0
to MA
3
.
Let us assume that normal word lines W
0
and W
1
are defective in memory array MA
0
, that a normal word line W
2
in memory array MA
1
is defective, and that a normal word line W
3
in memory array MA
2
is defective. In this state, the address of word line W
0
is programmed in spare decoder SD
0
, while the address of word line W
1
is programmed in spare decoder SD
2
. The address of normal word line W
2
is programmed in spare decoder SD
3
, and the address of normal word line W
3
is programmed in spare decoder SD
1
.
OR circuit G
0
selects one of spare word lines SW
00
, SW
10
, SW
20
and SW
30
, and the output signal of OR circuit G
1
selects one of spare word lines SW
01
, SW
11
, SW
21
and SW
31
.
When normal word line W
0
is addressed, the output signal of spare decoder SD
0
is driven into a selected state, and the output of OR circuit G
0
is activated. In this state, array address signal bits an-
2
and an-
1
activate row decoder X
0
, and the remaining row decoders X
1
to X
3
are maintained in a non-active state. Thus, a word line driving circuit included in row decoder X
0
drives spare word line SW
00
into a selected state in response to the output signal of OR circuit G
0
. At this time, in row decoder X
0
, a decode circuit provided corresponding to normal word line W
0
is maintained in a non-active state. As a result, defective normal word line W
0
is replaced with spare word line SW
00
.
If defective normal word line W
1
is addressed, the output signal of spare decoder SD
2
attains an H level in a selected state, the output signal of OR circuit G
1
attains an H level, and spare word line SW
01
is selected. If defective normal word line W
2
is addressed, the output signal of spare decoder SD
3
attains an H level in a selected state, the output signal of OR circuit G
1
attains an H level, and spare word line SW
11
is selected. If defective normal word line W
3
is addressed, the output signal of spare decoder SD
1
attains an H level in a selected state, and spare word line SW
20
is selected by OR circuit G
0
accordingly. More specifically, defective normal word lines W
0
, W
1
, W
2
and W
3
are replaced with spare word lines SW
00
, SW
01
, SW
11
and SW
20
, respectively.
In this flexible redundancy scheme shown in
FIG. 53
, a single spare word line can be activated by any of a plurality of spare decoders. For example, spare word line SW
20
can be driven into a selected state by spare decoder SD
0
or SD
1
. A single spare decoder can drive any of a plurality of spare word line into a selected state. For example, spare decoder SD
0
can drive any of spare word lines SW
00
, SW
10
, SW
20
and SW
30
into a selected state. Thus, the spare word line and spare decoders do not correspond in one-to-one relation, and therefore the spare word lines and spare decoders can be more efficiently utilized. The number of spare word lines and the number of spare row decoders in a single memory array may be selected independently from each other as long as the numbers satisfy the following relation:
L≦R≦M·L/m
wherein M is the number of physical memory arrays, m the number of memory arrays whose defective normal word lines are replaced with spare word lines simultaneously, R the number of spare row decoders, and L the number of spare word lines in a single memory array. More specifically, M/m is the number of memory arrays which are logically independent from one another. As a result, M·L/m represents the number of spare word lines which are logically independent from one another for the entire memory. Herein, the logically independent spare word lines are spare word lines selected by different row addresses. For example, in
FIG. 53
, if a normal word line is simultaneously selected in memory arrays MA
0
and MA
2
, memory arrays MA
0
and MA
2
are not logically independent from each other. In the arrangement shown in
FIG. 53
, L=2, R=4, M=4 and m=1.
By providing a spare row decoder common to memory arrays, a spare decoder does not have to be provided for each of spare word lines, which can restrain the chip area from increasing.
The flexible redundancy scheme shown in
FIG. 53
may be employed for repairing a defective column as well. In repairing a defective column, the previously mentioned prior art document describes a method of repairing a defective column where a memory array is divided into a plurality of sub-arrays. The document particularly describes the way of repairing a defective column in multi-divided bit lines in a shared-sense amplifier arrangement and i
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Andrew Q.
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