Processor

Details Processor Processor

1998-09-02

2001-01-09

Follansbee, John A. (Department: 2783)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C712S032000, C713S600000

Reexamination Certificate

active

06173408

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a processor having a data-dependent clock gating function.
Clock gating technique for stopping the supply of a clock signal to a circuit block in a processor when it is not necessary to operate the circuit block is known. In accordance with this technique, the power consumption of a processor can be reduced.
An image processing apparatus disclosed in Japanese Laid-Open Publication No. 8-65496 includes two circuit blocks. In each of a plurality of operation modes of the apparatus, the supply of a clock signal to at least one of the two circuit blocks is stopped. An operation mode signal, supplied from the outside of the image processing apparatus, specifies in which mode the apparatus should operate.
A microcomputer disclosed in Japanese Laid-Open Publication No. 5-324871 includes a central processing unit (CPU) and a plurality of peripheral hardware devices. Each of the peripheral hardware devices incorporates a core section and a clock controller. Each clock controller allows the supply of a clock signal to the associated core portion thereof only within a predetermined time zone between a time when the peripheral hardware device is selected by the CPU and a time determined by a timer.
A video encoder operating in compliance with an MPEG (Moving Picture Experts Group) standard includes a large number of operation units for motion prediction, DCT (discrete cosine transform), quantization, variable length coding and the like. It is known that the processing time of each such operation unit is dependent on image data. However, neither the conventional image processing apparatus nor the conventional microcomputer could perform data-dependent clock gating.
SUMMARY OF THE INVENTION
The object of the present invention is providing a processor having a data-dependent clock gating function.
In order to accomplish this object, according to the present invention, the operating status of an operation unit is monitored by an operation controller and the supply of a clock signal to the operation unit is allowed only while the operation unit is actually operating.
Specifically, the processor according to the present invention includes an operation unit, a microcontroller, an operation controller and a clock controller having the following functions. The operation unit is a unit having the functions of performing operation processing on data and supplying a status signal representing the status of the operation processing. The microcontroller has the function of generating an operation initiating signal. The operation controller is a controller asserting a request signal when the operation controller receives the operation initiating signal generated from the microcontroller, determining whether or not the status signal supplied from the operation unit satisfies a predetermined end condition, and negating the request signal if the status signal satisfies the end condition. The clock controller is a controller supplying a clock signal to the operation unit such that the operation unit can perform operation processing if the request signal has been asserted, and stopping the supply of the clock signal to the operation unit if the request signal has been negated.
According to the present invention, the time required for the operation unit to perform the operation processing is dependent on data. If the operation processing ends early, then the operation controller negates the request signal at early stage. Accordingly, the clock controller realizes data-dependent clock gating.


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