Method of fabricating passivation of gate electrode

Details Method of fabricating passivation of gate electrode Method of fabricating passivation of gate electrode

1999-06-08

2001-03-06

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000

Reexamination Certificate

active

06197673

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for fabricating passivation of a gate electrode, and more particularly, to a method to avoid a bridge in the gate electrode in the subsequent process for forming a contact window.
2. Description of the Related Art
In the conventional method for forming a gate electrode, a photoresist layer is used to transfer a pattern to an underlying nitride layer, tungsten silicide layer and a polysilicon layer. The photoresist layer is then removed. As long as the photoresist layer is sufficiently thick, the precision for the pattern transferring step can be retained. A cap layer is formed on the gate electrode, followed by forming a conformal liner oxide layer on the gate electrode. A spacer is formed on sidewalls of the gate electrode and the cap layer. While forming an opening within an oxide layer formed over the gate electrode, since the materials of the liner oxide layer and the oxide layer are the same, the liner oxide layer between the spacer and the gate electrode is to be removed consequently. When the opening is filled by a conductive material, a bridge between the conductive material and the gate electrode is caused to result a device failure. The yield of product is thus seriously affected.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating passivation of a gate electrode. A gate oxide layer, a conductive layer and a mask layer are formed. A patterned photoresist layer is formed on the mask layer. The photoresist layer is sufficient thick to precisely transfer a pattern to the mask layer. After patterning the mask layer, the photoresist layer is removed. Using anisotropic etching process, the patterned of the mask layer is transferred to the conductive layer to form a gate electrode. During the anisotropic etching process, a corner of the mask layer is partly truncated to form a cap layer with an arc shape corner. A conformal liner oxide layer is formed on a surface of the cap layer and a sidewall of the gate electrode. A spacer is formed on the liner oxide layer over sidewalls of the gate electrode and the cap layer. Due to arc shape corner of the cap layer, the spacer is formed to cover a part of the top surface of the cap layer, that is, from a cross sectional view, a distance between the topmost portion of spacer on two opposite sidewalls is smaller than the width of the gate electrode. The liner oxide layer between the spacer and the gate electrode is thus protected from being etched.
In another embodiment of the invention, in case the photoresist layer is not thick enough to obtain a precision transferred patterned as required, a distortion of the pattern is resulted. The distorted photoresist layer together with the patterned mask is served as a mask to pattern the underlying conductive layer to form a gate electrode. As a result, similar consequence is caused, that is, a cap layer with an arc shape corner is formed to cause a spacer extending over a top surface of the gate electrode, so as to protect the liner oxide layer formed between the spacer and the gate electrode from being etched.
Thus, in the invention, the mask layer has an arc shape corner to cause a spacer formed subsequently exceeding over a top surface of the gate electrode, so that a liner oxide layer formed between the spacer and the gate electrode is protected from being removed. The completeness of the gate electrode is thus retained. Since the liner oxide layer between the gate electrode and the spacer is protected from being removed, a bridge or even a short circuit between the gate electrode and a conductive plug formed subsequently is prevented from happening.
It is understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 4521448 (1985-06-01), Sasaki
patent: 4727038 (1988-02-01), Watabe et al.
patent: 5221632 (1993-06-01), Kurimoto et al.
patent: 5407848 (1995-04-01), Park et al.
patent: 5545578 (1996-08-01), Park et al.
patent: 5637514 (1997-06-01), Jeng et al.
patent: 5672525 (1997-09-01), Pan
patent: 5846873 (1998-12-01), Violette et al.
patent: 5972764 (1999-10-01), Huang et al.
patent: 5998289 (1999-12-01), Sagnes
patent: 6063681 (2000-05-01), Son

Affiliated with

Also associated with

Rating

Method of fabricating passivation of gate electrode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating passivation of gate electrode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating passivation of gate electrode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2550137