Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-30
2001-01-30
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S304000
Reexamination Certificate
active
06180973
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device and more particularly to a semiconductor memory device such as a DRAM with high integration density and a method for manufacturing the same.
With an increase in the integration density of a recent semiconductor integrated circuit, particularly a semiconductor memory device such as a DRAM (dynamic random access memory), the area of a memory cell tends to be reduced. Therefore, it becomes necessary to effect the fine patterning process and this increases the load on the lithography technology, and in the normal exposure technique, it becomes difficult to meet the requirement for the minimum processing size (which is hereinafter referred to as F) or the accuracy of alignment between patternings.
In order to alleviate the load for the lithography technology, the cell Layout having the same memory cell area and capable of alleviating the requirement for the minimum processing size is proposed. For example, in a DRAM memory cell constructed by one transistor and one capacitor, an area of 8×F
2
is required in the prior art if the minimum processing size (gate length) is set to F, but in the above memory cell, only an area of 4×F
2
to 6×F
2
is required. That is, since the memory cells of the same cell area can be processed with the larger minimum processing size, the load on the lithography technology can be reduced.
FIGS. 1A and 1B
show a memory cell having an area of 6×F
2
previously invented by the inventor of this application.
FIG. 1A
is a plan view of the memory cell and
FIG. 1B
is a cross sectional view taken along the line
1
B-
1
B of FIG.
1
A.
The memory cell is constructed by a cell transistor and a cell capacitor. The cell transistor has source and drain diffusion layers
71
a
,
71
b
formed on a semiconductor substrate
2
and a gate electrode
17
formed over the semiconductor substrate
2
with a gate insulating film
16
disposed therebetween and the gate electrode
17
constructs a word line. The cell capacitor is constructed by the semiconductor substrate
2
and a storage electrode
9
filled in an opening (trench)
7
formed in the semiconductor substrate
2
while a capacitor insulating film
8
is formed on the wall surface of the opening
7
and disposed between the wall surface and the storage electrode. The source or drain diffusion layer
71
a
of the transistor is connected to the storage electrode
9
of the capacitor via a connection electrode
73
and the other diffusion layer
71
b
of the transistor is connected to a bit line
24
via a bit line connection hole
23
.
With the memory cell shown here, even when the gate electrode
17
is first formed and then the diffusion layers
71
a
,
71
b
are formed in self-alignment with the gate electrode
17
, a certain area of the diffusion layer
71
a
can be stably obtained by setting the opening
7
in position shifted in a direction along the word line with respect to an element formation region
72
, and therefore, it becomes possible to set the opening
7
and the gate electrode
17
close to each other, thus making it possible to attain the area of 6×F
2
.
However, with the above structure, the diffusion layer
71
a
is formed to have a width which is half the width of the element formation region
72
in the word line direction and thus the width becomes substantially half the minimum processing size. Therefore, in order to obtain a certain area of the diffusion layer
71
a
, it is required to accurately control the processing dimensional precision and the accuracy of alignment between the patternings for the opening
7
and the element formation region
72
. For example, if the area of the diffusion region
71
a
varies or the area therefor cannot be obtained, the contact resistance between the storage electrode
9
and the diffusion layer
71
a
increases or varies, thereby making it difficult to attain a stable operation of the memory cell.
The above problem occurs not only in the memory cell having the area of 6×F
2
but also in a memory cell of other configuration such as a memory cell having an area of 8×F
2
.
Thus, in a conventional semiconductor memory device having an area of 6×F
2
or the like and a method for manufacturing the same, if the processing dimensional precision and the accuracy of alignment, between the patternings for the opening in which the storage electrode is to be filled and the element formation region in which the transistor is formed, are not sufficiently high, it becomes difficult to obtain a sufficiently large area for the diffusion region of the transistor and the connection resistance between the transistor and the storage electrode increases, thereby preventing the stable operation of the semiconductor memory device.
BRIEF SUMMARY OF THE INVENTION
An object of this invention is to provide a semiconductor memory device capable of obtaining a certain area for the diffusion region of a transistor and reducing the connection resistance between the storage electrode and the diffusion region of the transistor to attain the stable operation without receiving any influence of the accuracy of alignment of the patterning and a method for manufacturing the same.
In order to attain the above object, a semiconductor memory device according to a first aspect of this invention comprises a semiconductor substrate having a main surface; an element isolation insulating film formed on the main surface of the semiconductor substrate and buried in a first trench; a plurality of element formation regions each defined in an island form surrounded by the element isolation insulating film buried in the first trench; a plurality of second trenches formed in the plurality of element formation regions to be surrounded thereby, respectively; a plurality of capacitors formed in the plurality of second trenches, respectively, each of the capacitors having a plate electrode formed of the semiconductor substrate, a capacitor insulating film formed on an inner wall of each of the second trenches and a storage electrode formed in each of the second trenches with the capacitor insulating film disposed therebetween; a plurality of transistors formed in the plurality of element formation regions, respectively, each of the transistors having a gate electrode which is formed to extend over the semiconductor substrate and pass over corresponding one of the plurality of element formation regions and corresponding one of the second trenches surrounded thereby and which is disposed to be insulated from the storage electrode, corresponding one of the plurality of element formation regions and the semiconductor substrate, a first impurity diffusion layer formed on the corresponding one of the plurality of element formation regions on one side of the gate electrode, a second impurity diffusion layer formed on the corresponding one of the plurality of element formation regions on the other side of the gate electrode, and channel regions formed on the corresponding one of the plurality of element formation regions on both sides of corresponding one of the trenches below the gate electrode and respectively connected to the first and the second impurity diffusion layer; a plurality of connection electrodes each connecting the storage electrode to the first impurity diffusion layer; and a plurality of signal transmission lines each connected to the second impurity diffusion layer.
A semiconductor memory device according to a second aspect of this invention comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a semiconductor region formed on the insulating layer; an element isolation insulating film formed on the insulating layer to be connected thereto and buried in a first trench; a plurality of element formation regions each defined in an island form surrounded by the element isolation insulating film buried in the first trench; a plurality of second trenches formed in the plurality of element formation regions corresponding to the plu
Eckert II George C.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Saadat Mahshid
LandOfFree
Semiconductor memory device and method for manufacturing the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device and method for manufacturing the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and method for manufacturing the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2549045