Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-06-12
2001-03-06
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S104000, C710S105000, C710S107000, C710S117000, C710S123000, C710S241000, C710S070000, C710S036000, C710S038000, C710S113000, C370S402000, C709S232000, C713S400000
Reexamination Certificate
active
06199135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to storage interfaces in symmetrical multiprocessor systems, and more specifically, to a source synchronous transfer scheme that may increase the data rate over normal synchronous transfer methods.
2. Description of the Prior Art
In most general purpose, stored program, digital computers, it is desirable to have shared resources contained therein. Each of the shared resources may be designed to service a number of users. Possible shared resources may include a bus, a memory, a processor, or any other element within the computer system. The concept of utilizing shared resources has been used for several years to decrease the number of components within a computer system thereby increasing the cost effectiveness of the system. The use of shared resources also reduces the overall size and power requirements of the computer system.
Although these benefits can be substantial, shared resources may reduce the band pass of a system if not carefully used and designed. One reason for this is that only one of the users may use the shared resource at any given time. That is, the users must “share” the resource. Consistent therewith, computer designers must weigh the advantage of using a shared resource against the band pass limiting effect inherent therein. To increase the number of applications for shared resources and thus to take advantage of the benefits attributable thereto, computer designers have attempted to increase the band pass of shared resource designs.
One method for increasing the overall band pass of a shared resource design is to utilize priority schemes. For example, in a typical system, a number of processors may communicate with one another across a shared bi-directional bus. However, only one of the processors may use the shared bus at any given time. Therefore, the computer system must employ a mechanism for ensuring that only one processor has access to the shared bus at any given time while blocking access of the remaining processors.
Often, one or more of the processors may have a greater need to access the shared bus. One reason for this may be that one or more of the processors may be in the critical path of the computer system. If a processor is in the critical path of a computer system and it is not allowed to access the shared resource, the band pass of the entire computer system may suffer.
In a typical data processing system, there is a maximum of one data transfer per clock cycle. That is, data is typically transferred from a sending device to a receiving device on a leading or trailing edge of a system clock pulse. Thus, there is a direct relationship between the clock cycle time and the data transfer rate. Accordingly, data transfer rates are typically limited by the maximum clock rate of the system.
Several potential problems are encountered when increasing the maximum clock rate of the system. Transfers of data will typically occur between a transmitting and receiving component through two sets of latches. In order for the data to transfer successfully between the transmitting and receiving component, the data must traverse the path from the transmitting component latch to the receiving component latch within a set period of time, typically one clock cycle. Additionally the receiving latch requires the data to reach the input of the latch a certain period of time before the clock cycle occurs (typically referred to as “set-up” and “hold” times). Thus, timing constraints on the data transmittal path become more acute as the transfer clock rates are increased.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages associated with the prior art by providing a source synchronous transfer scheme between system components which enhances the transfer rate through the use of multi-phase data transfers within single clock cycle. Simply stated, the present invention allows more than one data transfer to occur on a single clock cycle. Thus, under the transfer scheme disclosed by the present invention, data transfer rates can be effectively doubled with no increase in the clock speed of the interface.
The transfer scheme of the present invention increases the transfer rate of the interface by multiplexing two data groups on the same interface. These data groups are transmitted from a source phase latch at approximately the same time as two strobe signals (a master and a slave) which have low skew with respect to the data. The master and slave strobe signals are logically combined to create an even latch enable signal and an odd latch enable signal that are used to latch and de-multiplex the multiplexed data groups at a receiving end of a pair of flow-though source synchronous latches.
The leading edge of the master strobe signal generates the leading edge of the even source synchronous latch enable signal, and the leading edge of the slave strobe signal generates the trailing edge of the even source synchronous latch enable signal. Similarly, the trailing edge of the master strobe signal generates the leading edge of the odd source synchronous latch enable signal, and the trailing edge of the slave strobe signal generates the trailing edge of the odd source synchronous latch enable signal. Using the leading and trailing edges of the latch enable signals to generate a clock source for the source synchronous latches at the receiving end ensures that the clocking signals are insensitive to signal attenuation caused by the transmission environment.
In a preferred embodiment, a data transmission from a source phase latch to a destination phase latch may be completed in one phase separation plus a clock pulse width. Clocking for the master and slave strobe signals will share common clock splitters with the data to minimize skew.
In a preferred embodiment, a Unisys hardware platform utilizes the source synchronous interface design of the present invention at four interface locations within the computer system. The interface of the present invention is used between the Main Storage Unit (MSU) and the Third Level Cache Memory Interface (TCM). This MI interface operates at a 100 MHz clock and 200 MHz data rate. The interface of the present invention is also used between the Third Level Cache Memory Interface Unit (TCM) and a Third Level Cache Module (TCT). This MT interface operate at a 133 MHz clock rate and a 266 MHz data rate. The interface of the present invention again is used between the Third Level Cache Memory Interface Unit (TCM) and the Direct I/O Bridge Unit (DIB). This MIO interface operates at a 50 Mhz clock and 100 Mhz data rate. Finally, the interface of the present invention is used between the Third Level Cache Memory Interface (TCM) and the cluster. This MIO interface operates at a 100 Mhz clock and 200 Mhz data rate.
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Accelerated Graphics Port Interface Specification, Revision 2.0
Bauman Mitchell A.
Maahs David A.
Malek Robert M.
Johnson Charles A.
Lee Thomas C.
Nawrocki, Rooney & Sivertson P.A.
Schuster Katharina
Starr Mark T.
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