Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-07
2001-07-17
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S471000, C257S486000, C438S237000, C438S581000
Reexamination Certificate
active
06262460
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a long-channel MOS transistor and, more particularly, to a long-channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor.
2. Description of the Related Art
An n-channel metal-oxide-semiconductor (MOS) transistor is a four-terminal device which controls the current that flows between two of the terminals by modulating the voltage which is applied to the third or fourth terminal.
FIG. 1
shows a cross-sectional diagram of a conventional n-channel MOS transistor
100
. As shown in
FIG. 1
, transistor
100
includes spaced-apart n+ source and drain regions
112
and
114
which are formed in a p-type substrate
110
, and a channel region
116
which is defined between source and drain regions
112
and
114
. Source and drain regions
112
and
114
, in turn, represent the first two terminals of the device while substrate
110
represents the third terminal.
In addition, transistor
100
also includes a layer of gate oxide
120
which is formed over channel region
116
, and a gate
122
which is formed over gate oxide layer
120
. Gate
122
represents the fourth terminal of the device.
In operation, electrons flow from source region
112
to drain region
114
when an electric field is established between source and drain regions
112
and
114
, the drain-to-substrate junction is reverse biased, and a gate voltage equal to or greater than the threshold voltage of transistor
100
is applied to gate
122
. These conditions can be met, for example, when ground is applied to substrate
110
and source region
112
, and one volt is applied to drain region
114
.
The gate voltage applied to gate
122
attracts electrons to the surface of substrate
110
in channel region
116
. When a minimum number of electrons has been attracted to the surface of substrate
110
in channel region
116
, the electrons form a channel which allows the electrons in source region
112
to flow to drain region
114
under the influence of the electric field. The threshold voltage defines the minimum gate voltage that must be applied to gate
122
to attract the minimum number of electrons to the surface of substrate
110
to form the channel.
The threshold voltage of transistor
100
is adjusted by implanting the surface of substrate
110
in channel region
116
with an p-type dopant which, in turn, decreases the number of available electrons at the surface of substrate
110
. Since fewer electrons are available, a higher gate voltage is needed to attract the minimum number of electrons that are required to form the channel.
MOS transistors are formed in a photolithograhpic process with a design rule that corresponds to the particular process being used. The design rule specifies, among other things, the minimum length of the channel region. To minimize the silicon area consumed by a MOS circuit, the circuit is largely implemented with transistors that have the minimum channel length.
Since the circuit is largely implemented with transistors that have the minimum channel length, the fabrication step that implants dopants into the surface of the substrate in the channel region is commonly optimized to adjust the threshold voltages of the transistors which have the minimum channel length.
One problem with this practice, however, is that circuits often require transistors which have channel lengths that are longer than the minimum. For those transistors with a longer channel length, a lower threshold voltage is realized when the threshold voltage is optimized for a shorter-channel transistor.
FIG. 2
shows a graph that illustrates threshold voltages versus channel lengths. As shown in
FIG. 2
, when the threshold voltage is optimized for a channel length x, the threshold voltage of a transistor decreases as the channel length of the transistor increases.
The reduced threshold voltages of the longer channel devices lead to increased leakage currents which, in turn, are particularly undesirable in circuits which are utilized in battery-operated devices.
One approach to this problem is to utilize multiple implant steps. In the first step, dopants are implanted into the surface of the substrate to adjust the threshold voltages of the short channel transistors while the long channel transistors are protected from the implant.
In the second step, dopants are implanted into the surface of the substrate to adjust the threshold voltages of the long-channel transistors while the short-channel transistors are protected from the implant. By utilizing two implant steps, the dopant concentration for the short and long channel lengths can be separately optimized.
The drawback to this approach, however, is that utilizing separate implant steps requires separate masks which, in turn, increases the cost of fabricating the circuit. Thus, there is a need for a long-channel MOS transistor which has a higher threshold voltage when the transistor is fabricated with a single threshold-voltage implant step that is optimized to set the threshold voltage of a short-channel transistor.
SUMMARY OF THE INVENTION
Conventionally, when the threshold voltage of a long-channel transistor is set during the same dopant step of a manufacturing process that optimizes the threshold voltage of a short-channel transistor, the process severely reduces the threshold voltage of the long-channel transistor. This reduction, in turn, leads to increased leakage currents. The present invention increases this reduced threshold voltage of the long-channel transistor by connecting the long-channel transistor in series with a schottky diode.
In accordance with the present invention, a threshold-voltage-adjusted transistor includes a first semiconductor material of a first conductivity type, and a second semiconductor material of a second conductivity type.
The threshold-voltage-adjusted transistor also includes a first transistor which is formed in the first semiconductor material. The first transistor has spaced-apart source and drain regions of the second conductivity type which are formed in the first semiconductor material, and a channel region which is defined between source and drain regions.
In addition, the first transistor also has a layer of gate oxide which is formed over the channel region, and a gate which is formed over the layer of gate oxide. The first transistor further has a channel length.
In accordance with the present invention, the threshold-voltage-adjusted transistor further includes a schottky diode which is formed in the second semiconductor material, and connected to the first transistor.
In addition, a second transistor, which has a channel length, is formed in the first semiconductor material. The channel length of the second transistor is substantially less than the channel length of the first transistor.
The present invention also includes a method for forming a circuit in a semiconductor material that has a first region of a first conductivity type and a second region of a second conductivity type. The method comprises the step of forming a short-channel transistor which has spaced-apart source and drain regions of the second conductivity type in the first region.
The method also includes the step of forming a long-channel transistor which has spaced-apart source and drain regions of the second conductivity type in the first region. The method further includes the step of forming a schottky diode. The schottky diode has a cathode formed by the second region, and an anode connected to the long-channel transistor.
The method additionally includes the step of doping the first region of the semiconductor material with a single masking step to set a threshold voltage in the first region. The threshold voltage is optimized for the short-channel transistor.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles
Bergemont Albert
Kalnitsky Alexander
Poplevine Pavel
National Semiconductor Corporation
Pillsbury & Winthrop LLP
Wojciechowicz Edward
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