Semiconductor memory device having redundancy circuit for...

Details Semiconductor memory device having redundancy circuit for... Semiconductor memory device having redundancy circuit for...

1999-02-25

2001-07-10

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700, C365S230060, C365S230080, C365S201000

Reexamination Certificate

active

06259636

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device, and particularly to a semiconductor memory device comprising a redundancy circuit for relieving faulty memory cell on a memory cell array.
Recently, further miniaturization of a memory cell has been promoted together with increase in a large capacity of a memory such as a dynamic RAM. If a memory cell is miniaturized, various faults easily occur. For this reason, it is difficult to normally operate a memory cell of the total bits and the yield of the good products is decreased. Thus, in general, a redundancy circuit for relieving a faulty memory cell is provided in a memory of a large capacity.
FIG. 7
illustrates an example of a schematic structure of a conventional semiconductor memory device comprising a redundancy circuit. A memory cell array
1
is constituted by aligning normal memory cells of predetermined capacity in a matrix of rows and columns. A redundant row
2
and a redundant column
3
are constituted by aligning redundant memory cells for relieving faulty cells that exist in the memory cell array
1
. A two-dimensional address space represented by an n-bit row address XA and an n-bit column address YA, both from the outside, is assigned to the memory cell array
1
.
In this example, each of the external row address XA and the external column address YA has a bit length of n bits, however the lengths of the addresses are determined in accordance with the capacity of the memory cell array
1
. The redundant row
2
, which relieves the row address XA from the fault, is constituted by one or a predetermined number of rows. The redundant column
3
, which relieves the column address YA from the fault, is also constituted by one or a predetermined number of columns.
A row decoding circuit
4
decodes the row address XA and selects the rows of the memory cell array
1
, and is constituted to drive X-address selection lines (word lines)
10
on the basis of the row address XA. A column decoding circuit
5
decodes the column address YA and selects the columns of the memory cell array
1
, and is constituted to select Y-address selection lines (bit lines)
11
on the basis of the column address YA.
In the normal write or read operations, a normal memory cell
9
located at a point of intersection of the X-address selection line
10
and the Y-address selection line
11
selected respectively by the row decoding circuit
4
and the column decoding circuit
5
, and the data read or write is carried out for the memory cell
9
.
A redundant row decoding circuit
6
selects the redundant row
2
, and is constituted to be activated by a replacement control circuit
8
-
3
described later and select an X-address selection line
10
a
of the redundant row
2
. A redundant column decoding circuit
7
selects the redundant column
3
, and is constituted to be activated by a replacement control circuit
8
-
4
described later and select a Y-address selection line
11
a
of the redundant column
3
.
When the redundant row
2
is selected by the redundant row decoding circuit
6
, a spare memory cell, i.e. a redundant memory cell,
9
ax
located at a point of intersection of the Y-address selection line
11
selected by the column decoding circuit
5
and the X-address selection line
10
a
of the redundant row
2
is accessed. When the redundant column
3
is selected by the redundant column decoding circuit
7
, a spare memory cell, i.e. a redundant memory cell,
9
ay
located at a point of intersection of the X-address selection line
10
selected by the row decoding circuit
4
and the Y-address selection line
11
a
of the redundant column
3
is accessed.
When the external row address XA coincides with a faulty row address stored in advance in the replacement control circuit
8
-
3
, the replacement control circuit
8
-
3
activates the redundant row decoding circuit
6
by a redundant row activation signal XRE. Similarly, when the external column address YA coincides with a faulty column address stored in advance in the replacement control circuit
8
-
4
, the replacement control circuit
8
-
4
activates the redundant column decoding circuit
7
by a redundant column activation signal YRE. The replacement control circuit
8
-
3
is operated independently of the column address YA, and the replacement control circuit
8
-
4
is operated independently of the row address XA.
The redundant row activation signal XRE from the replacement control circuit
8
-
3
is inverted by an inverter
30
and supplied to the row decoding circuit
4
so that the row decoding circuit
4
can be deactivated when the redundant row activation signal XRE is activated. The redundant column activation signal YRE from the replacement control circuit
8
-
4
is inverted by an inverter
31
and supplied to the column decoding circuit
5
so that the column decoding circuit
5
can be deactivated when the redundant column activation signal YRE is activated.
FIG. 8
illustrates an example of the structure of the replacement control circuits
8
-
3
and
8
-
4
. A memory circuit
14
stores selection information about use or non use of the redundancy circuit, and the faulty addresses, and comprises fuse circuits FE and F(
0
) to F(n−1) for respectively storing the selection information and the faulty addresses. Each of the fuse circuits is constituted by using, for example, a fuse, so as to store 1-bit data in response to the blown or non-blown state of the fuse. The fuse circuit FE stores the selection information of the redundancy circuit, and the fuse circuits F(
0
) to F(n−1) store the respective bit data of the faulty addresses.
An address coincidence detecting circuit
16
compares the respective bit data of the faulty addresses stored in the fuse circuits F(
0
) to F(n−1) with respective bit data Add(
0
) to Add(n−1) of external addresses, and activates and outputs a coincidence detection signal MATCH when the bit data coincide with one another. An AND circuit
17
operates a logic product of the selection information stored in the memory circuit
14
and the coincidence detection signal MATCH from the address coincidence detecting circuit
16
, and outputs an activation signal RE. That is, this replacement control circuit activates and outputs the activation signal RE when the faulty address coincides with the external address.
When the replacement control circuit shown in
FIG. 8
is used as the replacement control circuit
8
-
3
in
FIG. 7
, the information to select the use or non-use of the redundant row
2
is stored in the fuse circuit FE and the activation signal RE is taken as the redundant row activation signal XRE. When the replacement control circuit shown in
FIG. 8
is used as the replacement control circuit
8
-
4
in
FIG. 7
, the information to select the use or non-use of the redundant column
3
is stored in the fuse circuit FE and the activation signal RE is taken as the redundant column activation signal YRE.
For example, when the fault is relieved by using the redundant row
2
, “1” is written and stored as the selection information in the fuse circuit FE constituting the replacement control circuit
8
-
3
. Further, the respective bit data of the faulty row address is written in the fuse circuits F(
0
) to F(n−1). It is judged which of the redundant row
2
and the redundant column
3
should be used, in accordance with the generation scheme of the faulty cell (fault mode), and the desired data is stored in the replacement control circuit
8
-
3
or
8
-
4
.
In this case, the fuse circuit FE shown in
FIG. 8
serving as the replacement control circuit
8
-
3
outputs logic value “1”. The fuse circuits F(
0
) to F(n−1) output the respective bit data of the faulty row address as their output signals FOUT(
0
) to FOUT(n−1). The address coincidence detecting circuit
16
compares the bit data Add(
0
) to Add(n−1) of the row address from the outside with the bit data of the faulty address from the fuse circuits F(
0
) to F(n−1), and activates th

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