Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-22
2001-08-28
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S304000
Reexamination Certificate
active
06281535
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to capacitors and more particularly to a three-dimensional ferroelectric capacitor structure that can be utilized in a nonvolatile memory cell.
DESCRIPTION OF THE RELATED ART
Capacitors are widely used as storage elements in memory arrays fabricated on semiconductor substrates. Common dielectric materials utilized by the capacitors are silicon oxide (SiO
2
) and silicon nitride (Si
3
N
4
), which have dielectric constants of 4 and 7, respectively. However, due to the low dielectric constants of the silicon oxide and silicon nitride, the miniaturization of a capacitor with a dielectric material of either silicon oxide or silicon nitride is limited. The dielectric material of silicon oxide or silicon nitride is unable to maintain the required storage capacitance when the geometry of the capacitor is decreased below a minimal size. With the increase in demand for high-density memory devices with smaller memory cells, other dielectric materials have been researched as possible candidates to be used as capacitor dielectrics. The use of a ferroelectric material as the capacitor dielectric has emerged as an attractive approach to fabricating capacitors for high-ensity memory devices. The dielectric constant of a ferroelectric can range from 400 to as high as 1400. This implies that a 5 &mgr;m
2
dynamic random access memory (DRAM) cell could be reduced in size by as much as a factor of 20, using a ferroelectric dielectric capacitor structure.
Among the possible electrode materials for the ferroelectric dielectric capacitors, platinum (Pt) has become the most commonly used material. Platinum is highly conductive and tolerant to the processes of depositing and annealing the ferroelectric dielectric. In addition, ferroelectric lead-zirconate-titanate (PZT) devices using Pt electrodes exhibit low leakage current (<10
−9
amps/cm
2
). Moreover, Pt promotes the formation of PZT perovskite crystals with orientations which provide the best switching characteristics.
However, several fabrication complications are encountered in patterning the Pt electrodes and the ferroelectric capacitor dielectric. The etching of Pt to form the electrodes is a difficult process because of Pt's high inertness to chemical reaction, typically causing sputter etched Pt residue. The Pt residue can cause severe capacitor leakage. Moreover, the ferrous-electric dielectric is difficult to pattern by a single dry etch process. Multiple steps of patterning a resist layer and dry etching Pt or a ferroelectric material may be required to reduce the capacitor leakage.
A typical ferroelectric capacitor structure utilizes a two-dimensional structure that includes two flat parallel plates as the capacitor electrodes, with a ferroelectric dielectric material sandwiched between the plates. The structure is referred to as “two dimensional” because the height is solely a function of the thicknesses of the plates and dielectric material. That is, the length and width of a two-dimensional capacitor structure are configurable, but the height dimension is merely the sum of the layer thicknesses. For these capacitors, patterned dry etch processes of electrode material and/or ferroelectric material are essential to achieve capacitor cell definition. However, a more recently developed ferroelectric capacitor structure utilizes a three-dimensional structure, i.e., a capacitor structure having at least one layer with a nonplanar configuration.
An article by Kohyama et al., entitled “A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1Gbit DRAM and Beyond,” 1997
Symposium on VLSI Technology Digest of Technical Papers
, pp. 17-18, describes a three-dimensional capacitor structure having a ferroelectric dielectric material. The capacitor structure of Kohyama et al. is formed in a cavity in a layer of silicon nitride above a polysilicon plug. A first layer of ruthenium (Ru) is sputtered onto the silicon nitride layer and into the cavity such that the floor and sidewalls of the cavity are covered by the layer of Ru. The layer of Ru is then etched by a Chemical Mechanical Planarization (CMP) process, removing the portion of the layer of Ru outside the cavity. Thus, the layer of Ru is only present on the floor and the sidewalls of the cavity. This first layer of Ru in the cavity serves as the bottom electrode of the capacitor. Next, a ferroelectric dielectric material, barium-strontium-titanate (BST), and Ru are successively sputtered to form a layer of BST and a second layer of Ru. The second layer serves as the top electrode of the capacitor. The second layer of Ru is then patterned by an etch-back process to create a drive line for the capacitor.
Another three-dimensional capacitor structure of interest is described in U.S. Pat. No. 5,394,000 to Ellul et al. The Ellul et al. patent does not explicitly specify that a ferroelectric dielectric may be used as a possible dielectric material for the capacitor dielectric. Instead, silicon oxide is listed as the exemplary dielectric material. The capacitor of Ellul et al. is formed within an etched trench in a substrate. The trench has a main rectangular box-shaped region that is further extended by a smaller rectangular box-shaped region. To fabricate the capacitor of Ellul et al., a layer of dielectric material is deposited over the substrate, forming a cover layer on the bottom and sidewalls of the trench, as well as on surfaces outside the trench. Next, a first conductive layer is deposited above the layer of dielectric material to form the bottom electrode of the capacitor. The first conductive layer completely fills the smaller rectangular box-shaped region of the trench, leaving only a small rectangular trench in the main rectangular box-shaped region. The first conductive layer contained within the smaller rectangular box-shaped region serves as the storage node of the capacitor. A layer of capacitor dielectric material is then deposited over the first conductive layer. Lastly, a second conductive layer is deposited over the layer of capacitor dielectric material. The second conductive layer fills the remaining portion of the small rectangular trench to form the top electrode of the capacitor. Polysilicon is listed as an exemplary material for the conductive layers. After the deposition of the second conductive layer, a CMP process is used to planarize the resulting structure to the top of the trench in order to remove excess materials. The CMP process exposes the top and bottom electrodes and electrical contacts are patterned on the planarized surface for writing and reading electrical charges to and from the capacitor.
Although the known capacitor structures are well suited for their intended purposes, what is needed is a compact three-dimensional ferroelectric capacitor structure that can be efficiently fabricated utilizing a manufacturing process compatible with a conventional CMOS processing technology.
SUMMARY OF THE INVENTION
A capacitor structure or an array of capacitors and a method of fabricating the structure utilize the contours of a cavity created in a semiconductor layer stack to form two three-dimensional electrode plates. The three-dimensional electrode plates reduces the lateral size of the capacitor structure without a significant sacrifice of capacitance. The fabrication of the capacitor structure is compatible with a conventional CMOS processing technology, in which the resulting capacitor structure may be vertically aligned with a CMOS device. As an example, the capacitor structure may be fabricated along with a MOS pass transistor to form a one-transistor-one-capacitor nonvolatile memory cell having a U-shaped configuration that enables high cell density. The pass transistor forms the base of the U-shaped configuration and the two legs are paths from the source/drain regions. The capacitor structure is fabricated to form at least a portion of one of the legs. However, the capacitor structure may be used in other applications.
The three-dimensional capacitor structure
Eschbach Florence
Ma Shawming
Ray Gary W.
Agilent Technologie,s Inc.
Chaudhuri Olik
Peralta Ginette
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