Process for fabricating two different gate dielectric...

Details Process for fabricating two different gate dielectric... Process for fabricating two different gate dielectric...

1999-07-22

2001-03-13

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S303000, C438S305000

Reexamination Certificate

active

06200834

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for producing a semiconductor device, and more particularly to a method of reducing topography variation from a polysilicon mask using chemical mechanical polishing (CMP) operation in producing the semiconductor device.
2. Description of the Related Art
Merged dynamic random access memory (DRAM)-logic circuits (e.g., so-called “hybrid circuits”) offer possible advantages in terms of performance. However, thin gate dielectrics are required in the logic circuits to achieve high performance (e.g., higher speeds), whereas thick gate oxides are required in the DRAM arrays to achieve high yields.
In a conventional process, as described, for example, in U.S. Pat. No. 5,668,035, incorporated herein by reference, and as shown in
FIGS. 6A-6C
, a polysilicon mask is used to protect the thick gate dielectric in a DRAM Array while growing the thin gate dielectric in the logic circuits.
Specifically, as shown in
FIG. 6A
, using conventional photolithographic techniques a photoresist layer
18
is spin-coated on a first polysilicon layer
16
and patterned leaving portions of the photoresist over a memory device area
5
while exposing the polysilicon layer
16
over a logic device area
3
.
Then, the first polysilicon layer
16
is etched to the gate oxide layer
14
over the logic device area
3
, as shown in FIG.
6
A. The etching is performed using anisotropic plasma etching, for example, in a reactive ion etching (RIE), and using an etchant gas such as chlorine (Cl
2
) and a carrier gas, such as argon (Ar). This results in selective etching of the polysilicon layer
16
to the gate oxide
14
.
The first gate oxide layer
14
is selectively removed in the logic device area
3
using wet etching, for example, by dip etch in a dilute solution of hydrofluoric (HF) acid and water.
Referring now to
FIG. 6B
, the photoresist layer
18
is removed, a second gate oxide layer
15
, which is thinner than the first gate oxide
14
, is formed by thermal oxidation over the logic device area
3
. This thermal oxidation also forms a silicon oxide layer
17
on the polysilicon layer
16
, as shown in FIG.
6
B.
Referring now to
FIG. 6C
, a conformal second polysilicon layer
20
is deposited over the second gate oxide layer
15
in the logic device area
3
, and over the oxide layer
17
that was formed on the first polysilicon layer
16
during the thermal oxidation. Preferably, the second and first polysilicon layers,
16
and
20
, are deposited to essentially the same thickness. This provides for the concurrent etching of polysilicon layers
16
and
20
over the first and second gate oxide layers
14
and
15
, respectively, without resulting in over-etching one of the other device area into the silicon substrate
10
. The second polysilicon layer
20
is also doped with an N-type dopant by ion implantation. The independent doping of polysilicon layers
16
and
20
, from which the FET gate electrodes are formed, provides a means for independently controlling doping in both gate electrodes.
However, the above process results in a very non-planar structure. This nonplanarity will greatly reduce the process window for lithography at dimensions of 0.25 &mgr;m and below.
An additional problem is associated with forming self-aligned contacts in the array. This requires an SiN cap on top of the gates in the array. However, the SiN cap must be removed from the logic regions (e.g., SiN caps enhance diffusion through gate oxides, resulting in threshold voltage shifts for FETs) using an extra mask, thereby increasing the cost of the integrated circuit.
SUMMARY OF THE INVENTION
In view of the foregoing problems of the conventional methods, an object of the present invention is to provide a method for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP).
In a first aspect of the present invention, a method of making a semiconductor device, includes forming a substrate with a memory array region and a logic device region, growing a thick gate dielectric over the substrate, forming a gate stack, including a first polysilicon layer, over the thick gate dielectric for the memory array region, forming a thin gate dielectric on the substrate over the logic device region, wherein layers of the gate stack in the memory array region protect the thick gate oxide during the forming of the thin gate oxide, forming a second polysilicon layer for the gate stack in the logic device region, to produce a resulting structure, wherein a thickness of the second polysilicon layer is at least as thick as the gate stack in the memory array region, planarizing the structure using chemical mechanical polishing (CMP), and patterning the gate stacks in the memory array region and the logic device region.
With the method of the present invention, a planar structure is achieved for gate stack patterning. Additionally, a gate cap is formed in the array, which is required for self-aligned contacts, but not in the logic regions where the gate cap makes it more difficult to form dual work-function gates. Logic areas not covered by an SiN mask processing and provide dual work-function gates without the need of an extra blockout mask. The end structure is well-planarized, and gate stacks with different thicknesses are achieved with good controllability. That is, thin oxide gates and thick oxide gates can be obtained on the same chip.


REFERENCES:
patent: 5668035 (1997-09-01), Fang et al.
patent: 6015730 (2000-01-01), Wang et al.
patent: 6030876 (2000-02-01), Koike
patent: 6037222 (2000-03-01), Huang et al.

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