CMOS integrated circuit for lessening latch-up susceptibility

Details CMOS integrated circuit for lessening latch-up susceptibility CMOS integrated circuit for lessening latch-up susceptibility

1999-02-01

2001-05-08

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S371000, C257S369000, C257S373000, C257S376000

Reexamination Certificate

active

06229185

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit technology. More particularly, the present invention relates to a CMOS integrated circuit for lessening latch-up susceptibility.
2. Description of the Related Art
Although CMOS-based integrated circuitry is characterized by low-power consumption and high-density integration, devices such as transistors or resistors parasitic onto semiconductor substrates raise a reliability issue to be considered. Referring to
FIG. 1
, a conventional CMOS circuit fabricated onto a semiconductor substrate is schematically illustrated in a cross-sectional view. In the drawing, reference numeral
10
denotes a P-type semiconductor substrate in which an N-well
11
is provided. A PMOS transistor
12
is formed on the N-well
11
, whereas an NMOS transistor
13
is formed on the P-type semiconductor substrate
10
. An N-type doped region
14
and a P-type doped region
15
are formed in the N-well
11
and the P-type semiconductor substrate
10
to form the contact regions, respectively.
In
FIG. 1
, a pair of spaced apart P-type doped regions
12
S and
12
D serve as the source and the drain of the PMOS transistor
12
, while its gate
12
G is disposed to cover a portion of the N-well
11
between the source
12
S and the drain
12
D. A pair of spaced apart N-type doped regions
13
S and
13
D serve as the source and the drain of the NMOS transistor
13
, while its gate
13
G is disposed to cover a portion of the P-type semiconductor substrate
10
between the source
13
S and the drain
13
D. The PMOS transistor
12
is configured with the gate
12
G electrically connected to the gate
13
G of the NMOS transistor
13
to form an input terminal V
IN
, while the drains
12
D and
13
D are tied together to form an output terminal V
OUT
. Both the source
12
S of the PMOS transistor
12
and the N-type doped region
14
are powered by a voltage source V
DD
, and the source
13
S of the NMOS transistor
13
and the P-type doped region
15
is powered by another voltage source V
SS
.
As shown in
FIG. 1
, the source
12
S of the PMOS transistor
12
, N-well
11
, and P-type semiconductor substrate
10
constitute the emitter, base, and collector of a parasitic PNP bipolar junction transistor Q
1
, respectively. Moreover, the source
13
S of the NMOS transistor
13
, P-type semiconductor substrate
10
, and N-well
11
constitute the emitter, base, and collector of a parasitic NPN bipolar junction transistor Q
2
, respectively. In the drawing, R
W
designates one parasitic resistor spread over the N-well
11
, and R
SUB
designates another parasitic resistor spread over the P-type semiconductor substrate
10
.
However, when a voltage level higher than V
DD
or lower than V
SS
occurs at the output terminal V
OUT
on account of interference or noise, the emitter-base junctions of the parasitic transistors Q
1
and Q
2
will enter forward bias to conduct a current flowing therethrough. Even worse, the path between V
DD
and V
SS
is short-circuited so as to cause permanent damage to the integrated circuit. This is the so-called latch-up effect.
U.S. Pat. No. 4,947,227 discloses a latch-up resistant CMOS structure achieved by patterning a semiconductor substrate into a trench, on the inside surface of which an oxide insulating layer is thermally grown. Thereafter, amorphous silicon or polysilicon is deposited on the surface of the semiconductor and substantially fills the trench to form a well region. However, grain boundaries contained in the amorphous silicon or polysilicon will deteriorate the carrier mobility of transistors fabricated within such a well region.
In addition, U.S. Pat. No. 5,338,986 discloses a latch-up resistant CMOS output circuit achieved by increasing the source-gate spacing to dispose a resistance device at the source of the PMOS transistor or NMOS transistor and thus reduce the collector current of the parasitic transistor. However, U.S. Pat. No. 5,338,986 merely takes minority carriers into account, but secondary triggering induced by majority carriers results in a low holding-voltage and possibly a short-circuit of V
DD
-V
SS
causing permanent damage to the integrated circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a CMOS integrated circuit for lessening latch-up susceptibility.
The above object of the present invention can be accomplished with a CMOS integrated circuit. According to the present invention, the CMOS integrated circuit is formed on a P-type semiconductor layer and an N-type semiconductor layer in contact with the P-type semiconductor layer to establish a junction therebetween. A PMOS transistor is formed on the N-type semiconductor layer and configured with its source terminal connected to a first voltage source. An N-type contact region is formed in the N-type semiconductor layer and connected to the first voltage source. An NMOS transistor is formed on the P-type semiconductor layer and configured with its source terminal connected to a second voltage source. A P-type contact region is formed in the P-type semiconductor layer and connected to the second voltage source. Moreover, a P-type carrier-releasing region is provided with one portion formed in the N-type semiconductor layer and another portion formed in the P-type semiconductor layer to span the junction.
Therefore, the CMOS integrated circuit according to the present invention utilizes the P-type carrier-releasing region
27
as a majority-carrier guard ring as well as a minority-carrier guard ring. Even upon the occurrence of secondary triggering, higher holding voltage can be sustained because the P-type carrier-releasing region
27
acts as the majority-carrier guard ring. Therefore, V
DD
-V
SS
is not short-circuited and the integrated circuit is protected from permanent damage, thus lessening the latch-up susceptibility.


REFERENCES:
patent: 4152717 (1979-05-01), Satou et al.
patent: 4327368 (1982-04-01), Uchida
patent: 4947227 (1990-08-01), Teng
patent: 5083179 (1992-01-01), Chong et al.
patent: 5306939 (1994-04-01), Mitani et al.
patent: 5338986 (1994-08-01), Kurimoto
patent: 358218160 (1983-12-01), None

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