Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1997-09-30
2001-01-16
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S184000, C438S514000
Reexamination Certificate
active
06174756
ABSTRACT:
FIELD OF INVENTION
The invention generally relates to integrated circuits, and, more particularly, to the efficient formation of integrated circuits through the use of spacers to block deep junction implants and silicide formation in a region thereof.
BACKGROUND OF INVENTION
In the fabrication of integrated circuits (ICs) or chips, there are often conflicting requirements in different regions of the IC. Such conflicts increase the complexity of the fabrication process, resulting in the need for additional process steps.
This problem can be illustrated by the differing requirements in different regions of a memory IC such as a dynamic random access memory (DRAM) or merged DRAM-logic (embedded DRAM) chip. For example, deep junctions with self-aligned silicides (salicides) are desired in the support or logic regions to minimize series resistance. However, shallow junctions with low dose implants and no silicides are desired in the array in order to minimize junction leakage.
Conventional techniques of resolving such conflict in the array and support or logic regions require additional masking steps to block deep junction implants and silicide formation in the array. Such techniques add complexity and cost to the manufacturing process, as well as increase raw process time (RPT).
As apparent from the above discussion, it is desirable to provide a more efficient and simplified technique of addressing the conflicting needs of the different chip regions.
SUMMARY OF INVENTION
The invention relates to formation of devices with deep junctions without affecting devices with shallow junctions efficiently. In one embodiment, a substrate including as least first and second regions separated by an isolation region is provided. The first region comprising first device features that are separated by wide gaps and the second region comprising second device features separated by narrow gaps. The sides of the device features comprise spacers formed from a dielectric material. An interlevel dielectric layer is formed over the substrate to sufficiently fill the narrow gaps between the second device features in the second region. An etch is then performed to remove the interlevel dielectric layer from the top of the device features and surface of the substrate, while leaving second spacers over the first spacers on the sides of the first device features. Forming the second spacers with the layer used to fill the narrow spaces between the second devices enables an implant to form deep junctions in the first devices without additional mask steps since the second devices are protected by the interlevel dielectric layer. Since only the junction regions of the first devices are exposed, silicides can also be formed without additional mask steps.
REFERENCES:
patent: 5262655 (1993-11-01), Ashida
patent: 5773331 (1998-06-01), Solomon et al.
Alsmeier Johann
Bronner Gary
Gambino Jeffrey P.
Braden Stanton
Siemens Aktiengesellschaft
Tsai Jey
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