Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-24
2001-07-03
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S660000, C438S663000, C438S664000
Reexamination Certificate
active
06255214
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor device manufacturing, and more particularly, to the formation of low resistivity self-aligned silicide regions on the gate and source/drain junctions.
BACKGROUND OF THE INVENTION
In the manufacture of integrated circuits, a commonly used practice is to form silicide on source/drain regions and on polysilicon gates. This practice has become increasingly important for very high density devices where the feature size is reduced to a fraction of a micrometer. Silicide provides good ohmic contact, reduces the sheet resistivity of source/drain regions and polysilicon gates, increases the effective contact area, and provides an etch stop.
A common technique employed in the semiconductor manufacturing industry is self-aligned silicide (“salicide”) processing. Salicide processing involves the deposition of a metal that forms intermetallic with silicon (Si), but does not react with silicon oxide or silicon nitride. Common metals employed in salicide processing are titanium (Ti), cobalt (Co), and nickel (Ni). These common metals form low resistivity phases with silicon, such as TiSi
2
, CoSi
2
and NiSi. The metal is deposited with a uniform thickness across the entire semiconductor wafer. This is accomplished using, for example, physical vapor deposition (PVD) from an ultra-pure sputtering target and a commercially available ultra-high vacuum (UHV), multi-clamber, DC magnetron sputtering system. Deposition is performed after both gate etch and source/drain junction formation. After deposition, the metal blankets the polysilicon gate electrode, the oxide spacers, tile oxide isolation, and the exposed source and drain electrodes. A cross-section of an exemplary semiconductor wafer during one stage of a salicide formation process in accordance with the prior art techniques is depicted in FIG.
1
.
As shown in
FIG. 1
, a silicon substrate
10
has been provided with the source/drain junctions
12
,
14
and a polysilicon gate
16
. Oxide spacers
18
have been formed on the sides of the polysilicon gate
16
. The refractory metal layer
20
, comprising cobalt, for example, has been blanket deposited over the source/drain junctions
12
,
14
, the polysilicon gate
16
and the spacers
18
. The metal layer
20
also blankets oxide isolation regions
22
that isolate the devices from one another.
A first rapid thermal anneal (RTA) step is then performed at a temperature of between about 450°-700° C. for a short period of time in a nitrogen atmosphere. The nitrogen reacts with the metal to form a metal nitride at the surface of the metal, while the metal reacts with silicon and forms silicide in those regions where it comes in direct contact with the silicon. Hence, the reaction of the metal with the silicon forms a silicide
24
on the gate
16
and source/drain regions
12
,
14
, as depicted in FIG.
2
.
After the first rapid thermal anneal step, any metal that is unreacted is stripped away using a wet etch process that is selective to the silicide. A second, higher temperature rapid thermal anneal step, for example above 700° C., is applied to form a lower resistance silicide phase of the metal silicide. The resultant structure is depicted in
FIG. 3
in which the higher resistivity metal silicide
24
has been transformed to the lowest resistivity phase metal silicide
26
. For example, when the metal is cobalt, the higher resistivity phase is CoSi and the lowest resistivity phase is CoSi
2
. When the polysilicon and diffusion patterns are both exposed to the metal, the silicide forms simultaneously over both regions so that this method is described as “salicide” since the silicides formed over the polysilicon and single-crystal silicon are self-aligned to each other.
Titanium is currently the most prevalent metal used in the integrated circuit industry, largely because titanium is already employed in other areas of 0.5 micron CMOS logic technologies. In the first rapid thermal anneal step, the so-called “C49” crystallographic titanium phase is formed, and the lower resistance “C54” phase forms during the second rapid thermal anneal step. However, the titanium silicide sheet resistance rises dramatically due to narrow-linie effects. This is described in European Publication No. 0651076. Cobalt silicide (CoSi
2
) has been introduced by several integrated circuit manufacturers as the replacement for titanium silicide. Since cobalt silicide forms by a diffusion reaction, it does not display the narrow-line effects observed with titanium silicide that forms by nucleation-and-growth. Some of the other advantages of cobalt over alternative materials such as titanium, platinum, or palladium are that cobalt silicide provides low resistivity, allows lower-temperature processing, and has a reduced tendency for forming diode-like interfaces.
One of the concerns associated with cobalt silicide technologies is that of junction leakage, which occurs when cobalt silicide is formed such that it extends to the bottom and beyond of the source and drain junctions. An example of this occurrence is depicted in FIG.
3
. The source of this problem is roughness at the interface of the cobalt silicide and the silicon. The interface roughness arises out of line defects that are present in the silicon. Cobalt is the diffusing species in the initial reaction with silicon in a first annealing step to form the monosilicide, CoSi. The cobalt diffuses preferentially along the line defects, creating “spikes”, so that the interface of the CoSi and silicon (Si) is uneven. Hence, the thickness of the CoSi is not uniform, and extends deeper into the source and drain junctions where line defects are present. When a second annealing step is performed to form the lower resistivity phase disilicide CoSi
2
, the silicide extends even further downwards towards the bottom of the source and drain junctions, and possibly through them. The rough interface and spike formation causes CoSi
2
induced excess junction leakage. One way to account for this problem is to make the junctions deeper, so that the uneven silicide will not reach the bottom of the source and drain junctions. Making the junctions deeper, however, negatively impacts device performance.
SUMMARY OF THE INVENTION
There is a need for a method of producing ultra-shallow junctions while avoiding salicide-induced junction leakage.
This and other needs are met by embodiments of the present invention which provides a method of forming ultra-shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process. In this method, the gate and the source/drain junctions are first formed by doping a semiconductor material. A region of the formed gate and source/drain junctions are amorphized to form amorphous regions within the formed gate and source/drain junctions. A metal layer is then deposited over the gate and the source/drain junctions. Low resistivity metal silicide regions are formed on the gate and source/drain junctions by annealing.
By amorphizing regions of the gate and source/drain junctions prior to the silicidation process, a controllable interface between the silicide and the semiconductor material is achievable. A smooth interface between amorphous silicon and the crystalline silicon leads to a substantially smoother interface between the silicide and the silicon as compared to prior art processing. This avoids interface roughness and spike formation and thereby reduces or eliminates silicidation induced junction leakage. The controllable nature of the interface allows ultra-shallow junctions to be formed, since there is a reduced risk of the interface or spikes extending to the bottom of the source/drain junctions. The present invention thereby provides sufficient distance between the bottom of the silicide and the bottom of the source/drain junction so that there will be no junction leakage.
The earlier stated needs are also met by another embodiment of the present invention which provides a method of manufacturing a semiconductor device co
Besser Paul R.
Kepler Nick
Wieczorek Karsten
Advanced Micro Devices , Inc.
Elms Richard
Smith Bradley
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