Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1996-01-16
2001-08-07
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C713S503000
Reexamination Certificate
active
06272195
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to a method and apparatus of synchronizing signals at the system level interface and in particular to a device and method that compensates for signal propagation delays between portable computing devices and expansion units using the Peripheral Component Interface standard.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in connection with a portable computer system coupled to an expansion base unit housing one or more peripheral devices which are operably linked to the portable computer.
Standard bus architectures have been routinely employed as interfaces connecting the core microcomputer system to peripheral devices such as floppy disk drives, CD drives, printers, sound boards, tape backup systems, pointing devices and others for some time now. Popular examples of such bus architectures include the the Industry Standard Architecture (ISA), the Extended Industry Standard Architecture (EISA), the Micro Channel and NuBus. The introduction of advanced and higher speed computer systems, however, has created a need for an efficient high speed interface to communicate with peripheral devices. The response to this need was the development and adoption of the Peripheral Component Interface (PCI) standard.
A PCI bus is a synchronous, processor-independent 32-bit or 64-bit local bus that offers several key advantages over bus structures such a ISA and EISA. Compared to older architectures, PCI permits higher bus speeds (up to 33 Mhz), increased data transfer rates and independence from a particular processor or local bus arrangement.
Furthermore, PCI requires less printed circuit board (PCB) area compared to other bus implementations due to its relatively small pin count (49 pins for a Master PCI and 47 pins for a PCI target). Thus, it is common for computer manufacturers to offer one or more PCI slots on their desktop computers along side one or more ISA, EISA slots or other standard interface.
The use of the PCI architecture has been, until recently, primarily restricted to desktop computer systems. PCI use on portable systems such as laptops and notebook computers has been hindered for several reasons. First, portable systems have smaller PCB real estate limiting the size and quantity of circuitry. Second, since most portables operate on rechargeable batteries, any additional circuitry would drain available power, increase the frequency of battery recharge or replacement and divert power from other subsystems within the unit.
A popular addition to the portable computer system is commonly referred to as the expansion base or “docking” unit. In essence, a portable computer system is coupled to an expansion base via one or more physical connector(s) or via a single host bridge. The expansion base, in turn, houses one or more peripheral device such as a hard disk, sound card, video card and the like, which are driven by the portable computer's microprocessor.
SUMMARY OF THE INVENTION
The use of the PCI bus architecture on portable computer systems in conjunction with expansion base technology presents several difficulties. One such difficulty is conforming to the PCI defined standard of 2 ns (2×10
−9
) or less clock skew between any two devices on the bus. System clock skew is effected primarily by differences in wire lengths, capacitance, transit times and other system parameters relating to the physical layout on the system PCB.
While controlling the clock skew of devices within the larger desktop units is a relatively simple task, clock skew problems are a major concern for portable computer manufacturers looking to comply with the PCI clock skew tolerances. Limited PCB real estate, differences in system configurations, arrangement of PCB planes, signal routing paths, clock speeds and other factors specific to a given design are all critical factors effecting both the available design options and overall system clock skew.
Until the present invention, there was no practical cost effective means of compensating for differences in peripheral device clock skews without dedicating a critical area of the PCB or unnecessarily increasing component count.
Accordingly, it is one object of the present invention to provide a device for synchronizing clock signals at the physical interface level that brings peripheral clock signals out the portable PCI connector within the PCI clock skew specification. This is achieved by buffering the clock signals at the portable computer interface to cause a predetermined signal phase shift that aligns outgoing clock signals with a reference expansion bus clock signal.
Another object of the present invention is to provide a means of aligning signals that can be adjusted to compensate clock skew differences for a particular platform type or layout. The manufacturer computes clock skew differences either by theoretical or empirical techniques and components are then assembled at the portable unit's output and tuned to produce a desired amount of clock shift.
Yet another object of the present invention is to provide a cost effective means of compensating clock skews in a PCI based portable to expansion unit interface. Commonly available circuit components are arranged at the portable output stage in series with PCI device clock lines alleviating the need for special logic and/or large amounts of real estate. Power drain on system resources is kept to a bare minimum by implementing a passive circuit buffer array.
A device and method is disclosed for eliminating system clock skew between a portable computer unit and an expansion base using the PCI bus architecture as an interface. Included are an oscillator and an RC filter circuit tuned to a predetermined propagation delay time for aligning the portable subsystem clock signals with the expansion base clock signal at the expansion base connector. The device brings the overall clock skew for signals at the connector within clock skew tolerance specifications for the PCI bus architecture standard. Alternatively, a phase lead or lag relative to a reference clock signal may be obtained by using dedicated delay lines, or implemented in a semiconductor chip with programmable delay, or with other discrete or active components.
For a more complete understanding of the present invention, including its features and advantages, reference is now made to the following detailed description, taken in conjunction with the accompanying drawings.
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Brady III Wade James
Corrielus Jean B
Neerings Ronald O.
Pham Chi
Telecky , Jr. Frederick J.
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