Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output addressing
Reexamination Certificate
1998-06-02
2001-06-05
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output addressing
C710S120000, C711S001000, C711S202000, C711S220000
Reexamination Certificate
active
06243767
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to generally to host adapters for interfacing between I/O buses, and in particular to storage configurations in multi-tasking host adapters.
2. Description of Related Art
Prior single chip host adapters have been single task devices. For example, U.S. Pat. No. 5,659,690, entitled “Programmably Configurable Host Adapter Integrated Circuit Including a RISC Processor,” issued on Aug.19, 1997 to Stuber et al., which is incorporated herein by reference, had a single data channel connecting a SCSI bus with a host computer bus. An on-chip RISC processor, sometimes called a sequencer, managed all of the modules on the chip through a set of registers.
This host adapter was multi-tasking in the sense that multiple commands, each for a different SCSI target, could be in process at any given time. However, hardware in the host adapter could execute only one task at a time, such as transferring data from one SCSI target to the host computer. The sequencer managed the one task until either completion or interruption of the task. Upon completion or interruption of the task, the sequencer disabled the hardware and then reconfigured the hardware for a different task.
Since the hardware on the host adapter chip could execute only one task at a time, the sequencer on the chip managed only the one active task at a time. Consequently, there were long periods of time in which the sequencer was idle and waiting for an event such as the end of the data transfer. While the sequencer was capable of performing other tasks, the hardware limitations made such performance unusable.
A subsequent host adapter integrated circuit had two independent data channels that were managed by a single sequencer. One of the data channels could be transferring data between the host computer and SCSI buses, while the other of the data channels could be transferring administrative data such as I/O command blocks, scatter/gather lists, or command completions notifications to or from the host computer. In this host adapter integrated circuit, rather than wait for an event associated with one of the two data channels, the sequencer waited in an idle loop for an event in either to the two data channels. This permitted the sequencer to concurrently supervise active tasks in both the channels, and to provide timely service when required.
In this host adapter integrated circuit, each channel had its own unique set of registers, and also shared a set of registers common to both channels. Each unique set of registers had its own logical address space. This required two different sets of firmware routines for the sequencer, one associated with each channel, for tasks that were common to both channels, e.g., data transfers. While this host adapter integrated circuit was an improvement over the earlier one, the unique register set for each channel limited the expansion of the architecture unless space on the chip was allocated for a larger address space, which in turn required a larger command line for the sequencer, and more storage space for the command lines themselves.
SUMMARY OF THE INVENTION
According to the principles of this invention, a novel register architecture and register partitioning method facilitate high-speed concurrent processing within an integrated circuit that interfaces a first input/output (I/O) bus with a second input/output bus. In one embodiment, the register partitioning method includes assigning a register set in each of a plurality of modules of the integrated circuit an identical set of logical addresses. Each module in the plurality of modules is assigned a unique module identifier. A physical address is generated for a register in one of the register sets by combining a logical address for the register and the unique module identifier for the module containing the register.
Since the same logical addresses are utilized for each of the register sets, the number of logical addresses required is reduced relative to an implementation, which assigned each register set a unique set of logical addresses. Since the number of required logical addresses is reduced, the number of bits required to address a register is also reduced. This reduces the number of bits in a processor command line that is required to specify a source register, a destination register, or a combination of source and destination registers. The reduction in the number of bits in the processor command line reduces the silicon area required for the on-chip processor.
Another aspect of this invention further reduces the silicon area associated with the on-chip processor. According to the principles of this invention, a logical address is assigned to a register in a first register set where the register in the first register set is utilized in a first operation performed by the module containing the first register set. The same logical address is assigned to a register in a second register set where the register in the second register set is utilized in a second operation performed by the module containing the second register set. Here, the first and second operations are the same operation. As used herein, “same operation” does not mean a single operation at an instant in time, but rather refers generically to a type of process, such as a DMA transfer or pointing to a memory storage location that is performed independently by each module.
Since the logical register address definitions for the operation in each module are the same only a single firmware routine is required to perform the operation in each module. Conversely, as described above, when each module had different logical register addresses, a separate firmware routine was required for each module where the routines differed only in the logical register addresses used.
The combination of the reduction in the command line size and the reduction in the number of lines of firmware reduces the on-chip storage area required for the firmware. The width of the storage area is the width of command line, and the depth of the area is proportional to the number of command lines in the firmware. Since this invention reduces both of these factors, the invention reduces the on-chip storage area required relative to the prior art host adapters while supporting enhanced multi-tasking functionality.
According to the principles of this invention, an integrated circuit includes a first I/O bus interface circuit having a first register set. The integrated circuit also includes a second I/O bus interface circuit having a second register set; and a sequencer module that generates a physical address using a mode identifier in a mode select register and a logical address. An address bus couples the physical address to the first and second register sets. In one embodiment, the integrated circuit is a host adapter integrated circuit and in another embodiment is an I/O bus bridge integrated circuit.
REFERENCES:
patent: 3226694 (1965-12-01), Wise
patent: 3373408 (1968-03-01), Ling
patent: 3676852 (1972-07-01), Abernathy et al.
Adaptec, Inc.
Du Thuan
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
Lee Thomas
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