Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-11-03
2001-03-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S082000, C326S086000
Reexamination Certificate
active
06204684
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the field of integrated circuits and, more particularly, to integrated circuits used with digital devices. Specifically, the invention relates to method and apparatus of adjusting the slew rate dependent of the topology.
2. Description of the Related Art
Digital signals are generally defined as signals that have two states (e.g., a high state and a low state) in which the voltage level of each of the states is within its own predetermined range. For example, a signal in a high state may have a voltage level equal to approximately V
cc
, while a low voltage level may have a voltage equal to approximately V
ss
. Ideally, a transition between digital states occurs instantaneously, resulting in a vertical line that has an infinite slope. In actuality, a digital signal changes state over a specified period of time, providing a non-infinite slope that is equal to the time rate of change of the signal voltage. The time rate of change from one state to another state for a digital signal is defined as the slew rate, and it is typically measured in units of volts/time.
In computer systems, signals are generally transmitted throughout the system on a bus, which is a complex conglomeration of wire connections on which signals are applied. The operating frequency of the bus is a function of the output delay time, the flight time, the setup time, and the rise/fall time. All of the previously recited times, the are slew rate dependent. The flight time is the time it takes a signal to get from the output of an output buffer to the input of a receiver, which depends upon the slew rate. The rise/fall time, which also depends on slew rate, is the amount of time required to transition from one state to another state.
Generally, the faster the bus (i.e., the higher the operating frequency of the bus), the faster signals are transported along the bus, allowing for signals to be available for processing considerably earlier than they would otherwise have been. Assuming that a computer system can process these recently available signals, increasing the slew rate could increase the processing speed of the computer system.
As previously mentioned, a bus is the mechanism by which signals are transmitted throughout a computer system. The bus, for example, may be used to read and write information for a processor from and to a memory card. A bus configuration (i.e., topology) with connection devices only at both ends of the bus will allow a high slew rate and therefore a high operating frequency. Often, it is desired to add additional connection devices to a bus, such as, for example, a second processor card or a second memory card. In this case, the topology of the bus has been altered by connecting the additional load on the bus. One skilled in the art will appreciate that by connecting a “stub” to the bus, the slew rate at which the bus can operate will decrease. In today's computer systems the slew rate of devices connected to a bus is fixed for the worst possible configuration, i.e., in the example above, the slew rate of the processor and memory connection devices would always be permanently set to slow enough value to allow the insertion of a third or additional connection devices even if the default configuration has only the two minimally required connection devices. Thus, it would be beneficial to have a method and apparatus of adjusting the slew rate of devices connected to a bus dependent on the actual configuration of the bus.
SUMMARY OF THE INVENTION
An embodiment of the present invention relates to a slew rate control circuit. The invention includes two connection devices that are adapted to be coupled to two voltage supplies. The connection devices are connected to the bus by a select terminal of a signal application device. The signal application device has first and second positions which apply first and second amounts of resistance to the bus depending on the voltage on the select terminal. If an expansion board is adapted to be coupled to the bus, a different voltage is applied on the select terminal.
An alternative embodiment of the present invention relates to a method for reducing a slew rate which includes applying a resistive load to a bus corresponding to the number of logic circuits in a computer system. The number of logic circuits within the computer is varied by either adding or removing a logic circuit. A second resistive load is selected to be applied to the bus after the number of logic circuits in the computer system has been varied. The selection of a second resistance enables the amount of slew to be reduced.
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patent: 5559447 (1996-09-01), Rees
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patent: 5621335 (1997-04-01), Andresen
patent: 5751978 (1998-05-01), Tipple
patent: 5898321 (1999-04-01), Ilkbahar et al.
patent: 6049221 (2000-04-01), Ishibashi et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Le Don Phu
Tokar Michael
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