Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-26
2001-03-27
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S238000
Reexamination Certificate
active
06207564
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to the manufacture of semiconductor circuit devices. More particularly, the present invention is directed to a novel process which permits the formation of self-aligned polysilicon plugged contacts using nitride spacers and a polishing step to isolate the plugged contacts one from another.
2. The Relevant Technology
A challenge in current semiconductor design is the increasing pattern density and continuously smaller feature size during printing of DRAM arrays. This applies also for the printing and manufacturing of polysilicon plugs which are used in current DRAM technology to contact conductive layers e.g. the active area regions of a semiconductor to the conductive layers at a higher level.
In the current application this could be the connection between a source region of an access transistor in a memory cell to a tungsten plug of a bitline contact and the connection between the drain region of the access transistor to the storage container of the DRAM cell. Polysilicon plugs are required below every storage node and below every bitline contact.
The plugs have to meet two opposing requirements. Firstly, they have to be as large as possible to lower the electrical resistance and provide a good and easy alignment of the cell container or the bitline tungsten plug to the existing polysilicon plug. Secondly, they must be electrically isolated from each other, i.e. a space between the features during printing has to be maintained. Assuming all features are at minimum size, the space between the plugs has to be at the same size as the plug itself, which in turn limits the size of the plug.
One way to improve the situation is to print the polysilicon plug for the bitline contact with one mask and to print the polysilicon plugs for the cell containers using a different mask and alignment/exposure sequence. In this case, the pattern density is smaller and the polysilicon plugs can be enlarged without the risk of “photoresist scumming” during the exposure due to sub-minimum spaces between features. Highly accurate alignment becomes an important issue in this approach.
Consequently, it would be an advance in the art to overcome these problems by a creative processing sequence of masks, etchings, and order of fabrication process steps.
SUMMARY AND OBJECTS OF THE INVENTION
In the novel process flow taught herein for fabrication of dynamic random access memory structures, at least two masks are required for the manufacturing of polysilicon plugs. A first mask opens up contacts for the formation of polysilicon plugs to the drain of an access transistor above which a cell capacitor will be formed. The second mask opens up contacts for the formation of polysilicon plugs to the source of an access transistor above which a tungsten plug will be formed to connect to the bitline of the memory device. The second mask can also be used to plug NMOS devices in the periphery. If PMOS devices should be connected with a p-doped polysilicon plug, a third mask is required.
The first and second masks must be self-aligned to the edge of the access transistor in the array on the foundational silicon substrate of structure and also to the adjacent polysilicon plug so as to avoid shorts between polysilicon plugs and the access transistor, as well as between adjacent doped plugs to be formed. Such shorts are the result of misalignment between the plug masks or large line size variations of the first and/or second plug(s) to be formed.
In the inventive process, shorts between misaligned polysilicon plugs are avoided by surrounding at least one of the two polysilicon plugs with a thin isolating nitride spacer. The spacers are formed by isotropically depositing a thin nitride film and etching it back using a very anisotropic etch leaving only the vertical parts of the nitride film.
The nitride spacer is formed at the vertical wall of the contact hole after the contact hole is etched into the oxide but before the contact hole is filled with doped polysilicon, thereby surrounding the polysilicon plug laterally.
The possibility to self-aligning the two polysilicon plugs against each other permits printing of the polysilicon plug below the cell capacitor as well as the printing of the plug below the bit line contact which will be larger than as if the plug where printed at the same time. Isolation between the plugs is not obtained by line size control and accurate alignment, but rather by the surrounding nitride spacer sealing the plugs laterally against each other. This permits effective spacings between plugs down to 200 Angstroms which is the spacer thickness, rather than 3000 Angstroms which would be the photolithographic limit. Vertical isolation between the plugs is obtained by CMP steps or etchback of the plug forming polysilicon deposited to fill the contact openings.
Another aspect of depositing the doped polysilicon plugs at the contacts in two masking steps is that the printing of the first mask (e.g. the cell plate node plug) with the smallest feature size can take advantage of contacts having only one size. Further, the first mask which opens up contacts for the cellnode plugs is nearly identical to the mask defining the cell container. Additionally, the lithography needs to be developed only once for two layers, and alignment of the two layers is more readily accomplished if the printing is similar.
In furtherance of the advantage of depositing the doped polysilicon plugs at the contacts in two masking steps, it can be stated that the process integration can take advantage of the contacts opened by the first and second masks to improve the transistors in the periphery by using source/drain implants as well as punch through suppression implants after the second mask opens its respective contacts, while maintaining low leakage junctions at the cellnode side by not implanting into these areas late in the processing steps.
In an alternative embodiment of the invention process flow taught herein for fabrication of dynamic random access memory structures (DRAM), a third mask is required. The third mask opens up contacts to P-MOS devices of the periphery. Like the second mask described above (e.g. the bitline contact plug mask), the printing of the third mask is similar to a conventional gate mask.
The self-aligning aspect of the invention enables very small spaces between the polysilicon plugs printed at different mask levels. Thereby the unusable space is minimized and the present inventive method is an advance in the exploitation of memory area.
These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter
REFERENCES:
patent: 5700706 (1997-12-01), Juengling
Micro)n Technology, Inc.
Tsai Jey
Workman & Nydegger & Seeley
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