Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-11-08
2001-08-21
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S185020, C365S185280
Reexamination Certificate
active
06278642
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and more particularly, to limiting current drawn by memory cells during programming operations in nonvolatile memory integrated circuits, such flash electrically programmable and erasable read only memories.
BACKGROUND OF THE INVENTION
It is conventional to implement a memory system in an integrated circuit including an array of nonvolatile memory cells, such as flash memory cells, and circuitry for independently erasing selected blocks of the nonvolatile memory cells. A flash memory array circuit includes rows and columns of nonvolatile flash memory cells. Thus, each of the cells or storage locations of the flash memory array circuit are indexed by a row index and a column index.
Each column of cells of the flash memory array include memory cells with each cell being implemented with a floating-gate n-channel transistor. The drains of all transistors of a column are connected to a bitline, and the gate of each of the transistors is connected to a different wordline. The sources of the transistors are held at a source potential, such as ground, during a read or programming operation. Each memory cell is a nonvolatile memory cell since the transistor of each cell has a floating gate capable of semipermanent charge storage. The current drawn by each cell depends on the amount of charge stored on the cell's floating gate. Thus, the charge stored on each floating gate determines a data value that is stored semi-permanently in the corresponding cell. In a flash memory device, the charge stored on the floating gate of each cell is erasable by appropriately changing the voltage applied to the gate and source in a manner known in the art.
Typically, the cells of a flash memory array can be erased in blocks, such as boot blocks or sector-array blocks, or the entire integrated circuit chip can be erased at once using a bulk erase. Reads and writes are, however, typically performed on a random byte or word basis in conventional flash memory devices.
An example of a flash memory array is described in U.S. patent application Ser. No. 08/606,246, entitled “SEGMENTED NON-VOLATILE MEMORY ARRAY WITH MULTIPLE SOURCES WITH IMPROVED WORD LINE CONTROL CIRCUITRY,” filed on Feb. 23, 1996 and assigned to the assignee of the present application, which is herein incorporated by reference. .
The floating gate transistor is programmed by charge transport of electrons across a gate insulator onto the floating gate for storage. The floating gate transistor is erased removing the stored electrons from the floating gate and transporting these charges back across the gate insulator. The floating gate transistor is read by detecting a current, the conductance of which varies depending on whether or not electrons are stored on the floating gate.
One example of programming an n-channel floating gate field-effect transistor (FET) includes applying approximately +12 Volts between a select/control gate (control gate), which is capacitively coupled to the floating gate, and a source region of the FET. Approximately +6 Volts is applied between a drain region of the FET and the source region. Electrons are accelerated from the source region toward the drain region in a channel region formed between the source and drain regions. The electrons acquire kinetic energy, thereby freeing additional electrons that are accelerated toward the drain region. High energy “hot” electrons are attracted across the energy barrier of the gate insulator by the electric field resulting from the high voltage applied to the control gate. The electrons that accumulate on the floating gate raise a turn-on threshold voltage (V
T
) magnitude that inhibit current conductance between the drain and source regions when a read voltage is applied to the control gate during a read operation.
One example of erasing the n-channel floating gate FET includes applying approximately −10 Volts to the control gate, +5 Volts to the source region, and isolating (floating) the drain region of the FET. Electrons that were previously stored on the floating gate are removed from the floating gate by Fowler-Nordheim tunneling of the electrons across the underlying gate insulator. The V
T
magnitude is decreased toward its unprogrammed value, allowing current conduction between drain and source regions when a read voltage is applied to the control gate during a read operation.
Flash memory systems have been employed to emulate magnetic disk drive systems. Typically, the flash memory system is implemented as a card for insertion into a computer system with a chip set mounted on the card. The chip set includes an onboard controller and several memory chips controlled by the controller. Each memory chip implements an array of flash memory cells organized into independently erasable blocks.
Flash memory employed in mass storage applications, such as in systems that emulate magnetic disk drives, is typically very defect-tolerant. Row, column, block, and single-bit defects can be effectively mapped out of the memory system. These defects are stored in tables which are accessible by the controller. The storage of the defects in the tables substantially eliminates the need for on-chip redundancy which would otherwise occupy a large area of the chip die. Storage of the defects in the tables also permits a higher yield in manufacturing the memory chip set because more die can be produced per wafer due to the enhanced redundancy capabilities of the flash memory system.
The defect-mapped scheme can, however, complicate testing processes because defects need to be identified, mapped out, and stored in the controller-accessible tables. One example of a column defect is a row-column short. It is typically desired to program eight or more columns at a time, but a row-column short defect could draw excessive amounts of current preventing the flash memory cells in other columns from being programmed.
One solution to prevent defective columns from drawing excessive amounts of current during programming of the memory cells is to have the tester not program the defective columns. This solution, however, increases the tester costs and also complicates parallel testing because this solution requires a unique data pattern for each die under test.
There is a great industry-wide push to lower the power supply voltages for flash memory integrated circuits. As a result, typically all of the programming high voltages in a flash memory are internally generated with charge pumps. The charge pumps have a limited ability to supply current. Thus, a defective cell pulls down the internally-generated bitline supply voltage during programming operations.
For reasons stated above and for other reasons presented in greater detail in the Description of the Preferred Embodiments section of the present specification, there is a need for limiting the amount of current the defective cells draw during programing operations of non-volatile memory integrated circuits, such as flash memories.
SUMMARY OF THE INVENTION
The present invention provides a method and a memory integrated circuit having wordlines, bitlines, and an array of transistor memory cells. Each transistor memory cell is coupled to one of the bitlines and one of the wordlines. Current limiters are coupled to the bitlines such that each current limiter is coupled to one of the bitlines.
In one embodiment, each current limiter limits the amount of current that a defective transistor memory cell draws through the bitline coupled to the defective transistor memory cell. In one embodiment, the current limiters each comprise a current mirror circuit.
In one embodiment, the array of transistor memory cells includes floating gate transistor memory cells. In one embodiment, the current limiters are operated when data is programmed into the floating gate transistor memory cells.
In one embodiment, the current limiters are adjustable by trimming. In one embodiment, the current limiters can be disabled. In one embodiment, the current limiters ca
Chevallier Christophe J.
Lakhani Vinod
Elms Richard
Micro)n Technology, Inc.
Nguyen Vanthu
Schwegman Lundberg Woessner & Kluth P.A.
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