Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-09-01
2001-04-03
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C326S039000
Reexamination Certificate
active
06212670
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to field programmable devices, and methods of implementing logic circuits with them. More specifically, the application pertains to field programmable integrated circuits that include both look up tables and programmable logic array-like circuits.
BACKGROUND OF THE INVENTION
Combinational logic functions are basic building blocks of digital electronic circuits. As is well known, any combinational function can be specified as a boolean logic function of its inputs, and this function can be implemented in a logic circuit. By expressing boolean logic functions in sum of products (SOP) or product of sums (POS) form, it becomes a straightforward task to implement them with two-stage logic circuits (e.g., AND-OR, NAND-NAND, or NOR-NOR circuits). These two-stage circuits can be classified as product-term or Pterm-based circuits and can be implemented directly by electrically connecting those logic gates that are required to produce a desired function.
Programmable logic arrays (PLAs) are integrated circuits that can include multiple general-purpose product-term cells, which a designer can configure to implement specific combinational logic circuits. PLAs can be mask-based arrays that are permanently configured during semiconductor processing to form application-specific integrated circuits (ASICs). Alternatively, they can be field-programmable, which means that they can be electrically programmed and reprogrammed with relative ease. Generally, designers configure PLAs by defining current paths within the cells to obtain a product-term circuit that performs a desired logic function (e.g., by closing electrically erasable links). PLAs often use so-called wired-OR or wired-AND configurations to implement their second stages, and larger PLA-based integrated circuits, known as complex programmable logic devices, can include numerous AND-OR PLA-based blocks that typically have partially fixed OR planes.
The denser field programmable integrated circuits have generally been field programmable gate arrays (FPGAs), which have employed look-up tables (LUTs) based on static random access memory programming (SRAM) technology instead of product-term architectures. In LUTs, the input states address an entry in a user-defined table that contains a stored output value that corresponds to those input states for a desired function. Designers can rewrite the data in the table to define different logic functions. Some research has indicated that four or five input LUTs in FPGAs result in the best results in terms of chip area. Using LUTs of different sizes in an integrated circuit has also been proposed.
One important use for FPGAs is in prototyping and ASIC emulation. In addition, FPGAs can also be acceptable substitutes for smaller ASICs. But because FPGAs can have a significant programming overhead, even high capacity field programmable devices tend to be significantly slower and less area-efficient than ASICs. This can limit their usefulness in a variety of situations, particularly where cost and/or speed are significant considerations.
SUMMARY OF THE INVENTION
In one general aspect, the invention features a programmable monolithic integrated logic circuit that includes look up table circuits and programmable logic array-like circuits. The plurality of look up tables can be arranged in blocks that each occupy substantially the same area as each of the programmable logic array-like circuits. The integrated circuit can include a first number of the look up tables and a second number of the programmable logic array-like circuits and where the first and second numbers are related by a ratio of between 0.25:1 and 6:1, between 1:1 and 5:1, or about 4:1. The programmable logic array-like circuits can each include at least 10,000 or 50,000 equivalent two-input NAND gates, and the look up tables and the programmable logic array-like circuits can each comprise static random access cells.
The programmable logic array-like circuits can each include a first stage of logic gates having input lines operatively connected to the input lines of the programmable logic circuit and output lines, a second stage of logic gates having input lines and output lines operatively connected to the output lines of the programmable logic circuit, and a crossbar switch having input lines operatively connected to the output lines of the first stage and output lines operatively connected to the input lines of the second stage. The programmable logic array-like circuits can each include a first logic stage having input lines operatively connected to the input lines of the programmable logic circuit and output lines, a second logic stage gates having input lines and output lines operatively connected to the output lines of the programmable logic circuit, and a crossbar switch having input lines operatively connected to the output lines of the first stage and output lines operatively connected to the input lines of the second stage, where the crossbar switch includes switchable, unconnectable, and fixed connections between its input and output lines. The programmable logic array-like circuits can each include a first logic stage having input lines operatively connected to the input lines of the programmable logic circuit and output lines, a second logic stage having input lines and output lines operatively connected to the output lines of the programmable logic circuit, and a crossbar switch having input lines operatively connected to the output lines of the first stage and output lines operatively connected to the input lines of the second stage, where the crossbar switch comprises a programmable inverter operatively connected in a circuit path between one of the input lines and one of the output lines.
In another general aspect, the invention features a programmable logic circuit that includes a programmable inverter having an input electrically coupled to an output of a first logic stage, and a second logic stage having an input programmably electrically coupled to an output line of the programmable inverter and to one of the output lines of the first logic stage.
In a further general aspect, the invention features a method of implementing a logic circuit that includes reading a netlist that includes a plurality of subnets. The method also includes determining the suitability of ones the subnets to being implemented with look up tables and with programmable logic array-like circuits, and determining whether to implement each subnet with a lookup table or a programmable logic array-like circuit based on results of the step of determining. Based on the steps of determining, the method implements a first subset of the plurality of subnets with look up table circuits and a second subset of the plurality of subnets with programmable logic array-like circuits.
The method can include merging single input pterms in the programmable logic array-like circuits into one multi-input pterm and separating the subnets into high fan-in subnets and low fan-in subnets. The step of implementing can implement some of the subnets as a combination of look up table circuits and programmable logic array-like circuits. The method can also include repeating the steps of reading, determining the suitability, determining whether to implement, and implementing for a second netlist that includes a certain subnet that is the same as a certain one of the subnets in the first netlist, where the repeated step of implementing implements the certain subnet of the first netlist in a look up table and implements the certain subnet of the second netlist in a programmable logic array-like circuit. Furthermore, the method can also include providing stimulus to the look up table circuits and to the programmable logic array-like circuits and monitoring the response of the look up table circuits and the programmable logic array-like circuits to the stimulus.
This invention is advantageous in that it can permit a large number of logic circuits to be implemented efficiently. And because functions that are not efficiently implemented i
Agilent Technologie,s Inc.
Siek Vuthe
Smith Matthew
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