Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-06-20
2001-01-09
Teska, Kevin J. (Department: 2763)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S019000, C327S158000
Reexamination Certificate
active
06173432
ABSTRACT:
TECHNICAL FIELD
This invention relates to generating a sequence of accurately phased clock signals, and more particularly, to using delay and phase locked loops to provide a sequence of clock signals that are accurately phased relative to a master clock signal.
BACKGROUND OF THE INVENTION
Clock signals are used by a wide variety of digital circuits to control the timing of various events occurring during the operation of the digital circuits. For example, clock signals are used to designate when commands and other signals used in computer systems are valid and can thus be used to control the operation of the computer system. A clock signal can then be used to latch the command or other signals so that they can be used after the command or other signals are no longer valid.
The problem of accurately controlling the timing of clock signals for high speed digital circuits is exemplified by clock signals used in high speed dynamic random access memories (“DRAMs”) although the problem is, of course, also applicable to other digital circuits. Initially, DRAMs were asynchronous and thus did not operate at the speed of an external clock. However, since asynchronous DRAMs often operated significantly slower than the clock frequency of processors that interfaced with the DRAM, “wait states” were often required to halt the processor until the DRAM had completed a memory transfer. The operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a computer architecture known as “SyncLink.” In the SyncLink architecture, the system memory is coupled to the processor directly through the processor bus. Rather than requiring that separate address and control signals be provided to the system memory, SyncLink memory devices receive command packets that include both control and address information. The SyncLink memory device then outputs or receives data on a data bus that is coupled directly to the data bus portion of the processor bus.
An example of a packetized memory device using the SyncLink architecture is shown in FIG.
1
. The SyncLink memory device
10
includes a clock divider and delay circuit
40
that receives a master or command clock signal on line
42
and generates a large number of other clock and timing signals to control the timing of various operations in the memory device
10
. The memory device
10
also includes a command buffer
46
and an address capture circuit
48
which receive an internal clock signal ICLK, a command packet CA
0
-CA
9
on a command bus
50
, and a FLAG signal on line
52
. As explained above, the command packet contains control and address data for each memory transfer, and the FLAG signal identifies the start of a command packet which may include more than one 10-bit packet word. In fact, a command packet is generally in the form of a sequence of 10-bit packet words on the 10-bit command bus
50
. The command buffer
46
receives the command packet from the bus
50
, and compares at least a portion of the command packet to identifying data from an ID register
56
to determine if the command packet is directed to the memory device
10
or some other memory device
10
in a computer system. If the command buffer determines that the command is directed to the memory device
10
, it then provides a command word to a command decoder and sequencer
60
. The command decoder and sequencer
60
generates a large number of internal control signals to control the operation of the memory device
10
during a memory transfer.
The address capture circuit
48
also receives the command words from the command bus
50
and outputs a 20-bit address corresponding to the address data in the command. The address is provided to an address sequencer
64
which generates a corresponding 3-bit bank address on bus
66
, a 10-bit row address on bus
68
, and a 7-bit column address on bus
70
.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized memory device
10
shown in
FIG. 1
largely avoids this problem by using a plurality of memory banks
80
, in this case eight memory banks
80
a-h
. After a memory read from one bank
80
a,
the bank
80
a
can be precharged while the remaining banks
80
b-h
are being accessed. Each of the memory banks
80
a-h
receive a row address from a respective row latch/decoder/driver
82
a-h
. All of the row latch/decoder/drivers
82
a-h
receive the same row address from a predecoder
84
which, in turn, receives a row address from either a row address register
86
or a refresh counter
88
as determined by a multiplexer
90
. However, only one of the row latch/decoder/drivers
82
a-h
is active at any one time as determined by bank control logic
94
as a function of bank data from a bank address register
96
.
The column address on bus
70
is applied to a column latch/decoder
100
which, in turn, supplies I/O gating signals to an I/O gating circuit
102
. The I/O gating circuit
102
interfaces with columns of the memory banks
80
a-h
through sense amplifiers
104
. Data is coupled to or from the memory banks
80
a-h
through the sense amplifiers
104
and I/O gating circuit
102
to a data path subsystem
108
which includes a read data path
110
and a write data path
112
. The read data path
110
includes a read latch
120
receiving and storing data from the I/O gating circuit
102
. In the memory device
10
shown in
FIG. 1
, 64 bits of data are applied to and stored in the read latch
120
. The read latch then provides four 16-bit data words to a multiplexer
122
. The multiplexer
122
sequentially applies each of the 16-bit data words to a read FIFO buffer
124
. Successive 16-bit data words are clocked through the FIFO buffer
124
by a clock signal generated from an internal clock by a programmable delay circuit
126
. The FIFO buffer
124
sequentially applies the 16-bit words and two clock signals (a clock signal and a quadrature clock signal) to a driver circuit
128
which, in turn, applies the 16-bit data words to a data bus
130
. The driver circuit
128
also applies the clock signals to a clock bus
132
so that a device, such as a processor, reading the data on the data bus
130
can be synchronized with the data.
The write data path
112
includes a receiver buffer
140
coupled to the data bus
130
. The receiver buffer
140
sequentially applies 16-bit words from the data bus
130
to four input registers
142
, each of which is selectively enabled by a signal from a clock generator circuit
144
. Thus, the input registers
142
sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer
148
. The write FIFO buffer
148
is clocked by a signal from the clock generator
144
and an internal write clock WCLK to sequentially apply 64-bit write data to a write latch and driver
150
. The write latch and driver
150
applies the 64-bit write data to one of the memory banks
80
a-h
through the I/O gating circuit
102
and the sense amplifier
104
.
As mentioned above, an important goal of the SyncLink architecture is to allow data transfer between a processor and a memory device to o
Dorsey & Whitney LLP
Jones Hugh
Micro)n Technology, Inc.
Teska Kevin J.
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