Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-04-07
2001-01-30
Iqbal, Nadeem (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S757000
Reexamination Certificate
active
06182248
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to testing of bus fault isolation and recovery mechanisms and in particular to design verification of bus fault isolation and recovery mechanisms. Still more particularly, the present invention relates to error injection for design verification of bus fault isolation and recovery mechanisms.
2. Description of the Related Art
All data processing systems include busses, employed to transfer data to and from processors, memory controllers, memory, and input/output (I/O) devices. For various reasons, these busses are susceptible to errors such as electrical noises, imperfect connection, and the like. Various bus architectures provide for error detection and recovery in the event of such errors. As a result, error checking and recovery handling is typically built into the design of data processing system busses, generally in the form of address and data bus parity checking and error correction code (ECC) checking.
Error checking and handling recovery system designs must themselves be verified to ensure proper operation. Therefore, to ensure that error detection, capture, reporting, and correction facilities within fault isolation or recovery designs work as intended, design verification methodologies and tools are required which simulate errors likely to occur on a data processing system bus. The simulated errors should mimic the actual hardware errors which occur while the system is running typical software applications, and should work properly on all bus transactions supported by the bus architecture for which the error checking and recovery system being tested is designed.
Existing bus design verification tools are generally designed for the verification of bus functions for a given architecture, not particularly for verifying error detection and recovery mechanisms for a given design. Therefore such verification tools are prohibitively expensive and complex. Moreover, such verification tools are typically designed for one specific bus architecture, so that the fault isolation and recovery verification methodologies and tools are not applicable to other bus architectures. Finally, available tools are not capable of causing a single cycle, precise error.
It would be desirable, therefore, to provide a design verification mechanism for error detection and recovery facilities which is inexpensive, easy to assemble using off-the-shelf components, and very simple to use. It would further be advantageous for the methodology and tool utilized for design verification to be readily applicable to multiple bus architectures.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide improved method and apparatus for testing bus fault isolation and recovery mechanisms for data processing systems.
It is another object of the present invention to provide a method and apparatus for design verification of bus fault isolation and recovery mechanisms in data processing systems.
It is yet another object of the present invention to provide a method and apparatus for error injection for design verification of bus fault isolation and recovery mechanisms in data processing systems.
The foregoing objects are achieved as is now described. An error injection tool, connected to a bus to be tested in such a manner as not to interfere with normal operation, is employed for error detection and recovery design verification. The error injection tool is connected to the bus to be tested within a data processing system, the system is powered on, and applications simulating normal system loading are run. A desired error is then selected, and the error injection tool is actuated. The error injection tool monitors bus cycles and transactions through selected signals and, upon detecting an appropriate cycle or transaction, overdrives a selected conductor within the bus being tested to inject an error. The selected bus conductor is overdriven (forced) to a logic high or a logic low for a single clock cycle, simulating the intermittent nature of errors likely to occur during normal operation. Bus error signals are then monitored to ascertain whether the error was successfully injected. If not, subsequent attempts during appropriate bus cycles or transaction may continue until error injection is successful. Once an error is successfully injected, the operation of fault isolation and recovery facilities for the bus being tested may be observed to ascertain whether they are properly functioning. The error injection tool is inexpensive, readily built from off-the-shelf components, easily adaptable to a variety of bus architectures, and very simple to employ. A variety of different errors, such as address/data parity errors when different bus masters are driving the bus, may be selected for comprehensive verification of the error detection and recovery design.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4156132 (1979-05-01), Hazzard
patent: 4759019 (1988-07-01), Bentley et al.
patent: 4779271 (1988-10-01), Suzuki
patent: 4996688 (1991-02-01), Byers et al.
patent: 4999837 (1991-03-01), Reynolds et al.
patent: 5001712 (1991-03-01), Splett et al.
patent: 5008885 (1991-04-01), Huang et al.
patent: 5229999 (1993-07-01), Cushing et al.
patent: 5428624 (1995-06-01), Blair et al.
patent: 5561762 (1996-10-01), Smith et al.
patent: 5668816 (1997-09-01), Douskey et al.
patent: 5671352 (1997-09-01), Subrahmaniam et al.
Armstrong Cynthia Joan
Daniels Scott Leonard
Kitamorn Alongkorn
Oehlke Brian Anthony
Tonry Richard Martin
Emile Volel
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Iqbal Nadeem
LandOfFree
Method and tool for computer bus fault isolation and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and tool for computer bus fault isolation and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and tool for computer bus fault isolation and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2544148