Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-11-22
2001-03-20
Williams, Alexander O. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S737000, C257S778000, C257S780000, C257S693000, C257S692000, C257S774000, C257S691000, C361S774000, C361S777000, C174S260000, C174S261000
Reexamination Certificate
active
06204559
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a semiconductor package, and more particularly to a chip sized package (CSP) with an improved thin substrate for eliminating a die crack problem.
2. Description of the Related Art
As the need for lighter and more complicated semiconductor devices becomes greater semiconductor chips have become more and more complex thereby requiring more electrical connections. Therefore, the ball grid array (BGA) has been developed by the semiconductor chip packaging industry to meet these needs.
FIG. 1
depicts a conventional BGA semiconductor chip package
100
including a chip
101
attached on a substrate
102
having a dielectric layer
102
a
. The chip pads on the active surface of the chip
101
are connected to conductive traces
102
c
disposed on the upper surface
102
b
of the dielectric layer
102
a
by bonding wires
103
and the conductive traces
102
c
are electrically connected through the plated through holes (PTH)
107
to the solder ball pads
102
f
disposed on the lower surface
102
d
of the dielectric layer
102
a
. Each solder ball pads
102
f
has a solder ball
104
mounted thereon for electrical connection to outer circuit, such as a printed circuit board. A package body
105
encapsulates the chip
101
, bonding wires
103
and the substrate
102
.
The dielectric layer
102
a
of the substrate
102
is generally made of fiberglass reinforced bismaleimide-triazine (BT) resin, FR-4 fiberglass reinforced BT epoxy resin or polyimide and the thickness of the substrate
102
is about 0.56 mm. A copper die pad
108
is disposed on the central surface of the substrate
102
for carrying the chip
101
. The plated through holes (vias)
107
are arranged around the die pad
108
.
However, the overall volume of the above BGA semiconductor chip package
100
is too large to meet the packaging requirements for high density semiconductor chip. Accordingly, the packaging industry further develops a chip sized package (CSP) technology to meet the packaging requirements for high density semiconductor chip. Generally, the overall dimension of the chip sized package is smaller than 1.2 times of the chip dimension so as to increase the packaging density.
FIG. 2
illustrates a conventional CSP semiconductor chip package
200
including a chip
201
attached on a substrate
202
having a dielectric layer
202
a
. The chip pads on the active surface of the chip
201
are connected to conductive traces
202
c
disposed on the upper surface
202
b
of the dielectric layer
202
a
by bonding wires
203
and the conductive traces
202
c
are electrically connected through the plated through holes (PTH)
207
to the solder ball pads
202
f
disposed on the lower surface
202
d
of the dielectric layer
202
a
. Each solder ball pads
202
f
has a solder ball
204
mounted thereon for electrical connection to outer circuit, such as a printed circuit board. A package body
205
encapsulates the chip
201
, bonding wires
203
and the substrate
202
. According to the CSP semiconductor chip package
200
, the area surrounded by the solder balls is usually smaller than the area of the chip
201
.
According to the CSP semiconductor chip package
200
as shown in
FIG. 2
, the thickness of the substrate
202
is about 0.36 mm or less than 0.36 mm and the plated through holes (vias)
207
of the substrate
202
are arranged within the periphery of the chip
201
. At room temperature, the Storage Modulus (E') of the fiberglass reinforced bismaleimide-triazine (BT) resin for the substrate is about 7,000-9,000 MPa, while the Young's Modulus (E) of copper for the plated through holes (vias)
207
is about 110,000 MPa. During resin molding (about 175° C.), the Storage Modulus (E') of the BT substrate is about 2,000-3,000 MPa, while the Young's Modulus (E) of copper for the plated through holes (vias)
207
is about 103,000 MPa. Therefore, during resin molding (about 175° C.), the ratio of the copper's Young's Modulus (E) to the BT's Storage Modulus (E') increases from 15 to 500 such that the BT substrate
202
without vias
207
is relatively softer than the BT substrate
202
with vias
207
and the area of BT substrate
202
without vias
207
is unable to provide sufficient strength for supporting chip
201
. Besides, since the chip
201
is not supported by the die pad, in the CSP package, stress caused by molding pressure will exert on the edge
201
a
of the chip
201
and the chip will crack at the edge
201
a
area. This will lower the yield for production.
Accordingly, there is a need for the packaging industry for eliminating the die crack problem for the chip sized package.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a semiconductor package with an improved thin substrate in which the thin substrate is provided with an improved via hole arrangement for supporting the chip to eliminate the crack during molding process.
It is a secondary object of the present invention to provide a. a semiconductor package with an improved thin substrate in which the thin substrate is provided with a copper mesh for supporting the chip to eliminate the crack during molding process.
It is another object of the present invention to provide a semiconductor package with an improved thin substrate in which the thin substrate is provided with dummy via holes at the area under the chip edge for supporting the chip to eliminate the crack during molding process.
To achieve the above objects, the present invention shortens the length of outer traces on the substrate to move at least one outer via outwardly to a location under the edge of the chip so as to form an offset via. Since the via is made of copper, the offset via might provide sufficient supporting strength for the chip edge during molding process such that the die crack problem is eliminated. Further, the present invention also disposes a copper mesh on the substrate at the area without vias and traces so as to enhance the substrate strength for supporting the chip. When the chip is mounted on the substrate, the copper mesh lies under the edges of the chip for supporting the chip during molding process such that the die crack problem is eliminated.
According to another aspect of the present invention, dummy via holes are provided for the substrate at the area under the chip edge for supporting the chip. Since the dummy via holes are made of copper having sufficient supporting strength for the chip, the crack problem during molding process can be eliminated.
REFERENCES:
patent: 5581122 (1996-12-01), Chao et al.
patent: 5640047 (1997-06-01), Nakeshima
patent: 5640048 (1997-06-01), Selna
patent: 5796589 (1998-08-01), Barrow
patent: 5874784 (1999-02-01), Aoki et al.
patent: 5909054 (1999-06-01), Kozono
patent: 5945741 (1999-08-01), Ohsawa et al.
patent: 5959356 (1999-09-01), Oh
patent: 5962917 (1999-10-01), Moriyama
Chen Jian Wen
Lee Yire Zine
Lin Chun Hung
Tao Su
Advanced Semiconductor Engineering Inc.
Williams Alexander O.
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