Device which uses NOP command to share memory bus

Details Device which uses NOP command to share memory bus Device which uses NOP command to share memory bus

1999-03-16

2001-09-04

Dharia, Rupal (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S120000, C710S120000, C713S001000, C713S100000, C711S170000, C711S173000, C345S182000, C345S504000, C345S519000

Reexamination Certificate

active

06286069

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87120423, filed Dec. 9, 1998, the frill disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device which shares a memory bus. More particularly, the present invention relates to a device which uses a no operation (NOP) command to share a memory bus, which can reduce a size of a chipset and manufacturing costs of the chipset.
2. Description of the Related Art
FIG. 1
is a block diagram of a conventional computer architecture.
Referring to
FIG. 1
, a computer
100
includes a microprocessor
110
, a chipset
120
, a main memory
130
and a peripheral device
140
. The microprocessor
110
is a central processing unit (CPU) or a CPU and a circuit related to it. The chipset
120
is an integration of circuits in the computer
100
. The microprocessor
110
accesses data stored in the main memory
130
and communicates the data to the peripheral device
140
through the chipset
120
. The main memory
130
stores programs and data used by the microprocessor
110
. The main memory
130
includes synchronous dynamic random access memory (SDRAM). Commands used for SDRAM include precharge, read, write activate and no operation (NOP). The peripheral device
140
includes a hard disk, a floppy disk or a RS232 interface.
Although the circuit in the chipset can be complex in design to that it has many functions, the pin count of the chipset is limited by the size of the chipset.
In general, the chipset is a ball-grid array device having 492 pins. Two sets of control circuits are usually integrated into the device, in which one is a memory control circuit and the other is a graphic control circuit, to decrease manufacturing costs. However, the pin count of the chipset has risen to 556 as other peripheral control circuits have been integrated into the chipset. The manufacturing costs are increased and the size of the chipset is also increased.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a device which uses an NOP command to share a memory bus so that the problems of increasing the manufacturing costs and increasing the size of the chipset are avoided.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a device which uses an NOP command to share a memory bus. The device includes a chipset in which a peripheral control circuit and a memory control circuit are integrated. The peripheral control circuit and the memory control circuit share a plurality of pins in the chipset. A memory bus is connected to the chipset by the pins in the chipset. A peripheral device receives data sent from the peripheral control circuit through the memory bus. A drive circuit is connected to the memory bus. A main memory is connected to the memory bus.
The device according to the invention uses the NOP command to meet the function of multi-function Switching. When the drive circuit detects the NOP command pass through the memory bus, the drive circuit catches the NOP command and drives the peripheral device. When the microprocessor accesses the data stored in the main memory, the memory control circuit sends other commands to the main memory through the memory bus, and the drive circuit continuously detects the commands passing through the memory bus.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5659690 (1997-08-01), Stuber et al.
patent: 5953746 (1999-09-01), Crocker et al.
patent: 6148398 (2000-11-01), Chang et al.
patent: 6160561 (2000-12-01), Klein

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