Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-04-14
2001-04-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000
Reexamination Certificate
active
06222781
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of a semiconductor integrated circuit device for supplying power supply potential to an internal circuit in a test mode operation mode. More specifically, the invention relates to a structure of a semiconductor integrated circuit device having a power supply circuit which supplies to an internal circuit an externally applied arbitrary voltage in a test mode.
2. Description of the Background Art
With the enhancement of integration of a semiconductor integrated circuit device such as dynamic random access memory (hereinafter referred to as DRAM), for example, it becomes necessary to ensure the reliability of a scaled down transistor which constitutes the circuit device and to simultaneously satisfy requirements of the specification of an interface for data communication with any external unit of the semiconductor integrated circuit.
In general, the semiconductor integrated circuit device such as semiconductor memory is accordingly provided with a voltage-down power supply circuit which lowers external power supply potential Ext.Vcc to generate internal power supply potential int.Vcc.
Additionally, in the DRAM, the reliability of a memory cell capacitor constituting a memory cell should be assured and further the circuit structure should be implemented with consideration of the noise resistance in data reading as well as low power consumption and guarantee of the read voltage margin. Therefore, in the DRAM, half of the internal power supply potential int.Vcc is supplied to a cell plate which is an electrode opposite to a storage node of the memory cell capacitor and half of the internal power supply potential int.Vcc is also supplied as the precharge potential of a bit line pair.
In addition, a negative potential (substrate potential) is supplied to the substrate for the purposes of improvement in the leakage current characteristic of the transistor, reduction in the parasitic capacitance and the like.
The DRAM thus generally has a plurality of internal power supply circuits placed therein such as voltage-down power supply circuit, cell plate voltage generation circuit, bit line precharge voltage generation circuit, substrate potential generation circuit and the like, even if the externally applied external power supply potential Ext.Vcc is a single potential of 3.3 V, for example.
Those internal power supply circuits are designed to generate a stable potential level even if external power supply potential Ext.Vcc varies so as to ensure the stable operation of internal circuits. Meanwhile, some operation tests of a device require confirmation of the operation state of the device which occurs when the internal power supply potential is intentionally changed in a certain range in order to confirm the operation margin of the device. However, in the structure discussed above which converts external power supply potential Ext.Vcc and applies the resultant potential to internal circuits via the internal power supply circuits mentioned above, it is difficult to externally set the potential level generated by the internal power supply circuits at a desired value.
Further, as a screening test before shipment of, for example, the DRAM, an accelerated test which is so-called burn-in test is conducted. The purpose of this test is to reveal potential failures in a memory cell capacitor, a gate insulating film of a transistor, multilayer interconnection and the like by operating the device under accelerated conditions such as high voltage, high environmental temperature and the like. In such an accelerated test, not the potential generated by the internal power supply circuits but any desired power supply potential should be applied to the internal circuits.
FIG. 9
is a schematic block diagram illustrating a structure of a conventional potential supply circuit
8000
which enables an externally supplied voltage to be applied to an internal circuit instead of voltage generated by an internal power supply circuit in a semiconductor integrated circuit device.
Referring to
FIG. 9
, potential supply circuit
8000
includes a test mode signal generation circuit
8010
which generates active test mode signal STEST according to a combination of a control signal and an address signal which are supplied from the outside of the DRAM, a voltage application circuit
8040
which connects an internal power supply node ns to a terminal
8020
receiving an externally applied supply potential in response to activation of test mode signal STEST and electrically disconnects internal power supply node ns from terminal
8020
when the test mode signal is in the inactive period, and an internal power supply voltage generation circuit
8030
which supplies internal power supply voltage int.V to internal power supply node ns when test mode signal STEST is in the inactive period and stops the operation when the test mode signal is in the active period.
Internal power supply voltage generation circuit
8030
in
FIG. 9
represents any of the voltage-down power supply circuit, cell plate voltage generation circuit, bit line precharge voltage generation circuit, substrate potential generation circuit and the like.
The level of test mode signal STEST is herein at internal power supply voltage level int.Vcc in the active period and at ground potential level GND in the inactive period.
FIG. 10
is a circuit diagram illustrating a structure of voltage application circuit
8040
shown in FIG.
9
.
Referring to
FIG. 10
, voltage application circuit
8040
includes an inverter INV
500
operating at internal power supply voltage int.Vcc and receiving test mode signal STEST, a P channel MOS transistor P
502
and an N channel MOS transistor N
502
connected in series between external power supply voltage Ext.Vcc and ground potential GND, and a P channel MOS transistor P
504
and an N channel MOS transistor N
504
connected in series between external power supply voltage Ext.Vcc and ground potential GND.
Transistor N
502
receives at its gate signal STEST and transistor N
504
receives at its gate an output of inverter INV
500
. Transistor P
504
has its gate coupled to a connection node n
502
of transistors P
502
and N
502
and transistor P
502
has its gate coupled to a connection node n
504
of transistors P
504
and N
504
.
Voltage application circuit
8040
further includes a P channel MOS transistor P
506
and an N channel MOS transistor N
506
connected in series between external power supply voltage Ext.Vcc and substrate potential Vbb which is a negative potential, and a P channel MOS transistor P
508
and an N channel MOS transistor N
508
connected in series between external power supply voltage Ext.Vcc and substrate potential Vbb.
The gate of transistor P
506
is coupled to node n
504
and the gate of transistor P
508
is coupled to node n
502
. The gate of transistor N
508
is coupled to a connection node n
506
of transistors P
506
and N
506
and the gate of transistor N
506
is coupled to a connection node n
508
of transistors P
508
and N
508
.
Voltage application circuit
8040
further includes an N channel MOS transistor N
510
coupled between terminal
8020
and internal power supply node ns and having its gate potential controlled by the potential level of node n
508
.
An operation of voltage application circuit
8040
is now described briefly.
When test mode signal STEST attains an active state (“H” level: internal power supply voltage level int.Vcc), the output of inverter INV
500
attains “L” level (ground potential level GND). In response to this, transistor N
502
is set into the turn-on state while transistor N
504
is set into the turn-off state.
Accordingly, the gate potential of transistor P
504
is set at ground potential GND level by transistor N
504
and transistor P
504
attains the turn-on state. The potential level of node n
504
then reaches external power supply voltage Ext.Vcc. On the other hand, transistor P
502
remains in the turn-off state. The potential level of node n
502
is thus at g
Akamatsu Hiroshi
Matsumoto Yasuhiro
Lam David
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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