Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-30
2001-03-20
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S304000, C257S305000, C257S306000, C257S309000, C257S622000
Reexamination Certificate
active
06204527
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates generally to a semiconductor memory device and a method for producing the same. More specifically, the invention relates to a semiconductor memory device which is used as a random access memory (RAM) having trench capacitors.
2. Related Background Art
Currently, RAMs having trench capacitors as cell capacitors are widely used.
FIG. 22
shows a plan view of such a RAM, and
FIG. 23
shows a sectional view taken along line A—A of FIG.
22
. Memory cells connected to each bit line
50
are aligned with each other so that two adjacent memory cells serve as a set of memory cells. Cell transistors
30
1
, and
30
2
serving as components of the memory cells of the same set have a common drain
35
b
, to which the bit line is connected via a contact
55
(see FIG.
2
). To sources
35
a
, and
35
a
2
of the cell transistors
30
1
, and
30
2
, trench capacitors
60
1
, and
60
2
are connected. Gate electrodes
31
i
of the respective cell transistors
30
i
(i=1, 2) serve as word lines connected to the memory cells including the cell transistors
30
i
.
The trench capacitors of the adjacent set of memory cells connected to the same capacitor, e.g., the trench capacitors
60
1
, and
60
3
, are electrically isolated from each other by means of an insulator film
25
. The trench capacitors
60
1
,
60
2
and
60
3
of the memory cells connected to the same bit line are aligned with each other.
Over the respective trench capacitors
60
1
(i=1, 2, 3), pass-word lines
33
i
are provided. The pass-word lines
33
i
(i=1, 2, 3) serve as word lines for memory cells connected to a bit line adjacent to the bit line
50
, to which the memory cells including the trench capacitors
60
i
are connected.
FIG. 21
shows a sectional view of a memory cell of a conventional RAM having trench capacitors as cell capacitors of the memory cell. The RAM has a plurality of memory cells. Each of the memory cells has a cell transistor
30
and a trench capacitor
60
. The cell transistor
30
has a gate electrode
31
formed on a p-type silicon substrate
1
via a gate insulator film
29
, and a source region
35
a
and a drain region
35
b
which are n-type diffusion regions formed in the silicon substrate
1
so that the gate electrode
31
is sandwiched by the source region
35
a
and the drain region
35
b.
On the other hand, the trench capacitor
60
comprises a capacitor insulator film
7
formed on the wall surface of a trench provided in the silicon substrate
1
, a storage node
9
of a polycrystalline silicon film buried in the trench, a storage node electrode
41
of a polycrystalline silicon film formed on the storage node
9
, and a plate electrode
27
of an n-type diffusion layer formed in the silicon substrate
1
. Furthermore, n-type impurities are added to the polycrystalline silicon films forming the storage node
9
and the storage node electrode
41
.
The storage node electrode
41
is electrically connected to the source electrode
35
a
of the cell transistor
30
via a side wall contact
42
. Furthermore, on the side portions of the lower portion of the storage node electrode
41
, a thick insulator film
40
is formed to prevent a vertical parasitic transistor from being formed. On the upper portion of the storage node electrode
41
, an insulator film
44
is formed to electrically isolate the storage node electrode
41
from the pass-word line provided above the trench capacitor
60
. The trench capacitors of the adjacent memory cells are electrically isolated from each other by means of the insulator film
25
.
In the conventional RAM with the above described construction, since the thick insulator film
44
is formed in the upper portion of the trench capacitor
60
, the depth of the side wall contact
42
is great, so that the lower surface of the side wall contact
42
is arranged below the source region
35
a
. In such a state, a depletion layer of a p-n junction between a p-well
2
and the storage node
9
contacts the side wall contact
42
. Therefore, a leak current increases, so that the charge holding characteristic of the memory cell deteriorates. Furthermore, it is conceived that the depth of the source region
35
a
is increased in order to prevent the charge holding characteristic from deteriorating. In this case, there is a problem in that the punchthrough withstand voltage of the cell transistor
30
deteriorates.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor memory device which has a memory cell having a good charge holding characteristic without deteriorating the performance of a cell transistor, and a method for producing such a semiconductor memory device.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device comprises: a semiconductor substrate; a semiconductor region of a first conductive type formed in the semiconductor substrate; a diffusion region of a second conductive type different from the first conductive type, the diffusion region being formed on the surface of the semiconductor region; a trench formed in the semiconductor substrate so as to be adjacent to the diffusion region; a capacitor insulator film formed on a portion of a side surface of the trench, which extends from a position at a predetermined depth of the trench to a bottom portion of the trench, and on a bottom surface of the trench; a storage node formed so that a surface of the storage node buried in the trench has the same depth as that of the predetermined depth; a first insulator film formed in a portion of the side surface of the trench above the position of the predetermined depth of the trench, the first insulator having a window in a region contacting the diffusion region; and a storage node electrode formed on the storage node so as to bury the trench, the uppermost surface of a region of the storage node electrode contacting the diffusion region via the window being formed of a mono-crystalline silicon region.
Preferably, an MIS transistor is formed in the semiconductor region, and the diffusion region is one of the source and drain regions of the MIS transistor.
The thickness of an upper portion of the first insulator film on the side of the diffusion region is preferably less than the thickness of a lower portion of the first insulator film.
The semiconductor storage device may further comprise a second insulator film formed on the storage node electrode.
Preferably, the mono-crystalline silicon region and a region of a polycrystalline silicon are arranged on the uppermost surface of the storage node electrode in parallel, and the second insulator film comprises a third insulator film formed in the mono-crystalline silicon region, and a fourth insulator film formed in the polycrystalline silicon region, the fourth insulator film being thicker than the third insulator film.
The fourth insulator film is preferably buried in the storage node electrode.
Preferably, the MIS transistor has a gate insulator film which extends to a portion on the storage node electrode.
The gate insulator film is preferably a CVD oxide film or a silicon oxynitride film.
According to another aspect of the present invention, a method for producing a semiconductor storage device comprises the steps of: forming a trench in a mono-crystalline semiconductor substrate, in which a semiconductor region of a first conductive type is formed, so as to be adjacent to the semiconductor region; coating the inside of the trench with a capacitor insulator film; forming a storage node having an upper surface lower than the surface of the semiconductor substrate by burying a conductive material in the trench; forming a first insulator film on a side surface of the trench after removing the capacitor insulator film exposed to the side surface of the trench; forming a first conductive layer having an upper surface lower than th
Nitayama Akihiro
Sudo Akira
Sunouchi Kazumasa
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Wojciechowicz Edward
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