Planarization of LOCOS through recessed reoxidation techniques

Details Planarization of LOCOS through recessed reoxidation techniques Planarization of LOCOS through recessed reoxidation techniques

1998-11-12

2001-07-24

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S439000, C438S452000

Reexamination Certificate

active

06265286

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to fabrication of semiconductor devices and, more specifically, to a procedure for fabrication of field oxide.
2. Brief Description of the Prior Art
In the fabrication of semiconductor devices and particularly integrated circuits and with reference to
FIG. 1
a
, active or moat regions
23
are generally isolated from each other. This is accomplished by deposition of a hard mask
27
, generally in the form of a nitride, over silicon dioxide which grows over the wafer of semiconductor material with apertures being formed in the nitride in a predetermined pattern, generally by etching, down to the oxide on semiconductor material in the pattern of the isolation region. The wafer is then heated in an oxidizing ambient, preferably by steam, to grow a field oxide
21
in the unmasked or apertured regions of the mask. As the dimensions of the semiconductor components and particularly the moat regions and the field oxide regions have decreased and particularly when the active regions have dimensions of 0.4 microns and less, a nitride mask is required which has less bending capability than was used in the prior art, such prior art masks generally being about 1300 Angstroms in thickness over about 400 Angstroms of oxide. This has generally been accomplished by providing a thicker nitride mask of at least 1600 Angstroms and above and a thinner oxide mask of about 200 Angstroms. A problem with the use of the thicker nitride and thinner oxide mask is that, since there is essentially no bending of the nitride mask, the oxide formed, which has approximately twice the volume of the silicon which was used in its formation, grows straight up and creates regions of very high stress, particularly in those corner regions
29
where the enlarged volume of field oxide contacts the nitride mask. The nitride is then removed using a wet chemical etch process, this process initially using HF to remove any oxide that has been formed on the surface of the nitride during the thermal oxidation with subsequent removal of the nitride. Since the regions of high stress etch much more rapidly in HF than those regions not under stress and since HF is an etchant for silicon oxide, the oxide in the regions of high stress will be removed much more rapidly than the oxide formed on the unstressed or much less stressed field oxide. In addition, whenever the regions of oxide which are under high stress are subjected to HF during later processing, this will etch at a much faster rate than will any other unstressed and less stressed oxide regions. The result is that, after nitride removal, the field oxide
21
which defines the moat or active region
23
contains an escalloped region
25
where the high stress oxide existed and was removed by the HF as shown in
FIG. 1
b
. This results in a reduced usable flat surface region
13
on the field oxide as described.
A problem resulting from the reduced field oxide surface is that, in the subsequent processing, it is often necessary to provide a narrow slot over the field oxide which, with present technology, will have a pitch of 1.5 microns or less. Since the dimensions of the slot approach the width of the field oxide surface region
21
, it is important to maintain the flat portion
13
of the surface of the field oxide as wide as possible to provide tolerance for some misalignment of the slot. This tolerance requirement is diminished in the prior art due to the etching away of the portion
25
of the field oxide
29
under stress. It is therefore apparent that a technique is desirable which will retain the portion of the field oxide now removed and which will relieve the stress on the field oxide.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a technique for uniform formation of moat dimensions of 0.4 micron and less across a wafer. The benefits of this type of control are 1) the ability to control moat dimensions more easily without threat of over-etching oxide to expose the vertical edge of the moat (also known as creating a “shark's tooth”), 2) less oxidation under the moat nitride mask to reduce the hydrofluoric acid etch time necessary to remove this oxide during subsequent processing operations and 3) greater control of critical moat width across the wafer. In addition, the technique in accordance with the present invention planarizes the isolation oxide, thus eliminating the steep oxide sidewall which naturally occurs when using a 2000 Angstrom nitride mask. This is especially beneficial to 0.5 micron Flash EPROM devices which have a subsequent processing step in which polysilicon is etched away from the top of the field oxide. Critical alignment is necessary. Under standard processing conditions, slight misalignment can lead to filaments and other device problems.
Briefly, the above is accomplished by the use of a thin sacrificial oxide having a thickness of from about 10 percent to about 30 percent and preferably about 20 percent of the thickness of the desired final field oxide. Initially, the wafer is patterned with the nitride mask, etched and thermally oxidized as in the prior art for fabrication of LOCOS but for a shorter time than for standard LOCOS formation in order to provide the oxide with reduced thickness, the thickness of this oxide being from about 600 to about 1400 and preferably about 1000 Angstroms or about 20 percent of the thickness of the final field oxide for a device having a pitch of about 1.5 microns from active area to active area. This sacrificial oxide is removed with a hydrofluoric acid etch, leaving a recessed cavity in the silicon with some undercutting of the oxide under the nitride mask since the acid etch will also laterally etch some of the oxide beneath the nitride mask. Finally, the target field oxide is grown for isolation in standard manner. The resultant isolation is very planar and moat widths of 0.4 microns or less are very controllable.
The above described procedure is very simple compared with other prior art techniques for obtaining very small active areas and step height reduction of the isolation regions which require several addition processing steps as well as complicated etch techniques. The above described process does not require additional types of films as in the case of such techniques as poly-buffered LOCOS. In addition, the extra processing is complete in two steps, a thin oxidation and HF strip, so it does not add much cycle time to the process flow.


REFERENCES:
patent: 5726093 (1998-03-01), Yoo
patent: 5789305 (1998-08-01), Peidous

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