Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-19
2001-08-21
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S295000, C257S306000, C257S532000
Reexamination Certificate
active
06278153
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a thin film capacitor used as an element in various electronic circuits, and also to a wiring-patterned structure used in a wiring board.
2. Description of the Related Art
There has been know a single-layered thin film capacitor including a first electrode layer, a dielectric layer formed on the first electrode layer, and a second electrode layer formed on the dielectric layer, as suggested in Japanese Unexamined Patent Publication Nos. 5-226844, 8-88318 and 10-154878. There has been also known a thin film capacitor having a multi-layered substrate including a substrate, a ground layer formed on the substrate, a dielectric layer formed on the ground layer, and an electrically conductive layer formed on the dielectric layer, as suggested in Japanese Unexamined Patent Publication Nos. 7-30257 and 7-307567.
These thin film capacitors are generally designed to include an upper electrode, a lower electrode, and a dielectric layer sandwiched between the upper and lower electrodes, and are accompanied with the following problems.
The first problem is that the upper electrode is liable to short-circuit with the lower electrode.
FIG. 1A
is a cross-sectional view of a thin film capacitor. The illustrated thin film capacitor is comprised of a substrate
90
, a lower electrode
91
formed on the substrate
90
, a dielectric layer
92
formed on the lower electrode
91
, and an upper electrode
93
formed on the dielectric layer
92
.
If the thin film capacitor is properly fabricated in such a configuration as designed, the thin film capacitor would have such a structure as illustrated in FIG.
1
A. However, if the upper electrode
93
is formed out of place, for instance, the upper electrode
93
would make contact with the lower electrode
91
, resulting in occurrence of short-circuit between the upper electrode
93
and the lower electrode
91
, as illustrated in FIG.
1
B.
The upper electrode
93
may be designed to have a width smaller than a width of the lower electrode
91
in order to avoid such short-circuit, which, however, would cause a problem that a capacitor has to be formed in a greater size for ensuring a desired capacity. This results in reduction in a density of wiring. In order to avoid reduction in a capacity of a capacitor, it would be necessary to re-design a capacitor with respect to configuration thereof.
The second problem is that it is difficult to form multi-layered wirings in the above-mentioned capacitor having a multi-layered structure. A multilayered wiring substrate including a thin film capacitor therein is formed with via-holes in order to electrically connect electrodes of thin film capacitors formed in upper and lower layers, to each other.
As such a via-hole, there are known a filled via-hole as shown in Japanese Unexamined Patent Publication No. 7-30257 and a postless via-hole as shown in Japanese Unexamined Patent Publication No. 7-307567. A filled via-hole is used more widely than a postless via-hole. This is because that a filled via-hole can vertically connect an electrode formed in an upper layer to an electrode layer formed in a lower layer to thereby increase a wiring density.
However, when a filled via-hole is formed in the above-mentioned capacitor having a multi-layered structure, it is unavoidable that there is formed a step having a height in the range of 2 to 20 &mgr;m between the upper and lower electrodes. As a result, there is also formed a step or irregularity on an outer surface of a resultant thin film capacitor. Thus, it is quite difficult to properly form a power-feeding layer absolutely required for formation of a filled via-hole.
FIG. 2
illustrates a thin film capacitor in which this problem is caused. The illustrated thin film capacitor is comprised of a substrate
94
, a lower electrode
95
, a dielectric layer
96
formed on the lower electrode
95
, an upper electrode
97
formed on the dielectric layer
96
, and a power-feeding layer
98
covering the upper electrode
97
, the dielectric layer
96
and the lower electrode
95
therewith. A filled via-hole
99
is formed above the upper electrode
97
.
As illustrated in
FIG. 2
, the lower electrode
95
is liable to be reverse-tapered when patterned. As a result, there is formed a step between the substrate
94
and the lower electrode
95
, which would cause breakage of the power-feeding layer
98
. Thus, a filled via-hole is liable to be improperly formed.
Though Japanese Unexamined Patent Publication No. 10-154878 has suggested a solution to this problem, the suggested solution is accompanied with another problem that fabrication steps become unavoidably complicated.
The third problem is that the above-mentioned capacitor having a multi-layered structure is fabricated through a quite complicated fabrication process. This is because it is necessary in the process to carry out film deposition and film patterning for each of electrode layers and a dielectric layer.
The fourth problem is that a dielectric layer is sometimes deteriorated in quality during a thin film capacitor fabrication process.
A dielectric layer is patterned generally through a dry etching step and a washing step for removal of etching residue. Removal of etching residue has to be absolutely carried out for enhancement in reliability of a thin film capacitor. In general, acid is selected for washing in order to sufficiently wash a dielectric layer. However, since etching residue is composed mainly of a material resulted from reaction between a dielectric material of which a dielectric layer is composed and etching gas, acid which is capable of dissolving etching residue can dissolve the dielectric layer. As a result, the dielectric layer is partially reduced in a thickness or is subject to alteration in composition.
This problem as mentioned above occurs when a dielectric layer is patterned by wet etching through the use of acid, as well as when a dielectric layer is patterned by dry etching. Furthermore, the above-mentioned problem remarkable occurs when a dielectric layer is composed of perovskite-structured material such as BST (Ba
X
Sr
1-X
TiO
3
), PZT (PbZr
X
Ti
1-X
O
3
), PLZT (Pb
1-Y
La
Y
Zr
X
Ti
1-X
O
3
) and SrBi
2
Ta
2
O
9
. Such perovskite-structured material is preferably used to a need for fabricating a capacitor in a smaller size with a higher capacity. However, if such perovskite-structured materials washed with acid, particular ingredients are dissolved out, which would cause alteration in composition. The materials having perovskite-structure have electricity characteristic which significantly varies due to even small alteration in composition, resulting in that the above-mentioned problem becomes remarkable.
On the other hand, conventional methods of forming an electrically conductive wiring can be grouped into a subtractive method and an additive method. A subtractive method is a method in which an electrically conductive wiring is formed by etching a copper foil formed on a substrate or a resin. For instance, Japanese Unexamined Patent Publication No. 10-51105 has suggested one of such subtractive methods. An additive method is a method in which an electrically conductive wiring is formed by electroless plating or electroplating.
The above-mentioned additive method may be grouped further into a semi-additive method as suggested in Japanese Unexamined Patent Publication No. 9-64493 and a full additive method as suggested in Japanese Unexamined Patent Publication No. 6-334334. A semi-additive method is a method in which an electrical conductor is formed in a resist film by electroplating after formation of a power-feeding layer, and, after removal of the resist film, the power-feeding layer is etched into a wiring pattern. A full additive method is a method in which a resist film is patterned after a substrate has been activated at a surface thereof, and an electrical conductor is formed by electroless plating with the resist film being used as a mask.
The above-mentioned subtractive and semi-additive method
Kikuchi Katsumi
Matsui Koji
Shibuya Akinobu
Shimoto Tadanori
Fenty Jesse A.
Lee Eddie C.
NEC Corporation
Young & Thompson
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