Self-aligned, low contact resistance, via fabrication process

Details Self-aligned, low contact resistance, via fabrication process Self-aligned, low contact resistance, via fabrication process

2000-04-03

2001-06-12

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S672000

Reexamination Certificate

active

06245657

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to improve the contact between a metal interconnect structure, and an underlying conductive plug structure, located in a via hole.
(2) Description of Prior Art
Micro-miniaturization, or the use of sub-micron features, has allowed the semiconductor industry to improve device density, resulting in improvements in device performance, and reductions in processing costs for a specific semiconductor device. The sub-micron features have in part been obtained via advancements experienced in the photolithographic discipline, such as the use of more advanced exposure tools, as well as the development of more sensitive photo sensitive materials. The use of sub-micron features can however in some cases, give rise to yield and performance degradations, not encountered with counterpart devices fabricated using larger features. For example the situation in which an upper level metal interconnect structure is designed to overlay, and contact, a portion of a metal plug structure, located in a via hole, which in turn allows electrical communication between the upper level metal interconnect structure, and a conductive region, underlying the metal plug structure, can be adversely influenced by sub-micron features, as well as by shrinking ground rules. The margin or error, encountered via misalignment of the upper level metal interconnect structure to a portion of the metal plug structure, may be difficult to contain when employing the sub-micron features achieved using advanced photolithographic procedures. This type of mis-alignment can lead to high resistance, performance problems, or even yield degrading opens, between metal interconnect structures.
This invention will describe a novel process sequence which allows self-alignment, and greater contact between metal interconnect structures, connected by a recessed metal plug in a via hole. Prior art such as Lee et al, in U.S. Pat. No. 5,956,609, as well as Wang et al, in U.S. Pat. No. 5,994,213, describe methods used to fabricate metal plug structures, however these prior arts do not described the metal ring structure, on a recessed plug structure located in a via or a contact hole, featured in this present invention.
SUMMARY OF THE INVENTION
The invention features the simultaneous formation of a metal interconnect structure, comprised of an upper level metal interconnect structure, and comprised of an attached metal ring, or metal shunt structure. The metal ring component of the metal interconnect structure is located around the inside perimeter of the via hole, thus overlaying and contacting portions of the underlying metal plug structure, providing self-alignment of the metal interconnect structure to the underlying metal plug structure, located in a via hole, and also providing increased contact area between these structures. Mis-alignment between the upper level metal interconnect structure, and the metal plug structure, is more easily tolerated as a result of the attached metal ring component, located in the via hole. The ability to tolerate mis-alignment allows the trend of using sub-micron features, and shrinking ground rules to continue, and to be used for sub-micron devices in static random access memory, (SRAM), cells, or other high density logic or memory cells.
It is an object of this invention form a metal interconnect structure that self-aligns to an underlying metal plug structure, located in a via hole.
It is another object of this invention form a metal interconnect structure, with an attached metal ring, or an attached metal shunt component, which is located overlying a portion of a recessed metal plug structure, which in turn is located in a via hole.
It is another object of this invention to recess a metal plug structure in a via hole, allowing deposition, and anisotropic etching of an overlying metal layer, to form a metal ring component for a metal interconnect structure, with the metal ring component located around the inside perimeter of the via hole, overlying a portion of the underlying recessed metal plug structure, in the via hole.
In accordance with the present invention a method of fabricating a metal interconnect structure, self-aligned to an underlying, recessed metal plug structure, featuring a metal ring component, of the metal interconnect structure, overlying and contacting a portion of the underlying, recessed metal plug structure, is described. A metal plug structure is formed in a via hole, with the metal plug structure overlying and contacting a lower level metal interconnect structure. After recessing of the metal plug structure in the via hole, a metal layer is deposited on the top surface of an insulator layer, in addition to coating the sides of, but not filling, the top portion of the via hole, that is not occupied by the recessed metal plug structure. A photoresist shape, and an anisotropic reactive ion etching, (RIE), procedure, are used to define an upper level metal interconnect structure comprised of a metal interconnect component, located on the top surface of the insulator layer, and to define an attached metal ring component, located overlying, and contacting portions of the underlying metal plug structure.


REFERENCES:
patent: 5472912 (1995-12-01), Miller
patent: 5834369 (1998-11-01), Murakami et al.
patent: 5956609 (1999-09-01), Lee et al.
patent: 5994213 (1999-11-01), Wang et al.

Affiliated with

Also associated with

Rating

Self-aligned, low contact resistance, via fabrication process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned, low contact resistance, via fabrication process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned, low contact resistance, via fabrication process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2541678