Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-08-26
2001-07-03
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
Reexamination Certificate
active
06256227
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory, and more specifically, to a layout of a column selector of the non-volatile semiconductor memory having a double (two-layered) bit line structure for use in e.g., a flash EEPROM (electrically erasable programmable read-only memory).
In the semiconductor memory, in most cases, a word line and a bit line are divided in order to attain a high-speed read-out operation.
Particularly in a flash EEPROM, when a data rewrite operation to a certain memory cell is performed, other memory cells which share the same bit line or word line with the target memory cell, are placed in a semi-selection state, with the result that data stored in the other memory cells are altered. This phenomenon is called “disturbance during a data-rewrite mode”. To prevent such a phenomenon, a memory cell array is divided into a plurality of blocks (cell-blocks) so that the word lines and bit lines of a block to be subjected to an erase operation can be electrically isolated from those of another block.
Generally, each cell block is constructed so as to have 512K bits (64K bites) constituting 1K word line×512 bit lines or 512 word lines×1 bit line. A row decoder and a column decoder are respectively divided into a plurality of row sub decoders and a plurality of column sub selectors, corresponding to a plurality of cell blocks.
Now, we will explain a column decoder of a conventional flash EEPROM.
In the flash EEPROM, the column selector, to which a selection signal is supplied from the column decoder, is constituted of a plurality of column sub-selectors which are arranged in every cell block of 512 K bits. The column sub-selectors are arranged in a discrete form. Size of a memory chip is influenced by the manner how to arrange wiring layers between the column sub-selectors. Furthermore, if a memory capacity increase, the number of cell blocks is inevitably increased, resulting in an increase of wiring resistance between column sub-selectors. To prevent such an increase in wiring resistance, a double-layer metal wiring (generally, aluminum wiring) has been generally employed as the wiring layer between the column sub-selectors.
FIG. 5
shows an equivalent circuit of part of a conventional NOR-type flash EEPROM employing a double bit line architecture which consists of double-layered aluminium wiring layers formed in a column direction of the memory cell array.
In
FIG. 5
, a plurality of cell blocks
51
i
(i=1 to n) are arranged in a column direction of a memory cell array. In each of the cell blocks
51
i
, a plurality of cell transistors CTs constituting 512K bits are arranged in a matrix form.
In each of the cell block
51
i
, sub-word lines SWLs are arranged in a row direction. To each of the sub word lines, control gates of the cell transistors CTs belonging to the corresponding row are connected in common. Sub-bit lines SBLs are arranged in individual columns in the column direction. To each of the sub-bit lines, drains of the cell transistors CTs belonging to the corresponding row, are connected in common. To sources of the cell transistors CTs within each of the cell blocks
51
i
, a common block source line BSL is connected.
Main bit lines MBLs are extended in the column direction of the memory cell array. To each of the main bit lines MBLs, sub lit lines corresponding to a plurality of cell blocks
51
1
to
51
n
are connected in common.
Each of the column sub-selectors
52
i
(i=1 to n) is extended at one side of the corresponding cell block
51
i
in the column direction (vertical direction in FIG.
5
). In each column sub-selector
52
i
, a plurality of block selection transistors (bit line selection transistor) (BSTs) are arranged in the row direction for selecting the corresponding sub-bit lines SBLs of the cell block
51
i
.
In the column sub-selector
52
i
, each of a plurality of block selection transistors BSTs is connected between the sub bit line SBL of the corresponding cell block
51
i
and the corresponding main bit line MBL. Further, a block decode line BDL is extended in the row direction. To the block decode line BDL, the transistor BST gates are connected in common.
The main bit lines MBLs are collectively connected at each of one end thereof via the corresponding Y selection transistor (column selection transistor) CST. The main bit lines MBLs thus connected are further connected to a write load transistor (not shown), a sense-amplifier (not shown) and the like.
The column selection transistors CSTs are independently driven by a main column decoder (not shown). The block decode lines BDLs are independently driven by a block decoder and a column sub-decoder (not shown). The sub word lines SWLs are independently driven by a column sub-decoder (not shown). The block source line (BSL) is set so as to have a predetermined potential by a block source decoder (not shown) in accordance with an operation mode.
With the aforementioned construction, the sub bit lines arranged in every cell block are electrically isolated from those of other cell block by each of the column sub-selectors
52
i
.
In the aforementioned example, a single main bit line is arranged per single sub bit line. However, in some cases, a single main bit line is arranged per a plurality of sub bit lines. Furthermore in the aforementioned example, a plurality of column sub-selectors is arranged in parallel per single main bit line. In some cases, a single column sub-selector may be connected to a single main bit line.
FIG. 6
is an example of a practically and conventionally used pattern layout surrounding a column sub-selector
52
1
for attaining the circuit shown in FIG.
5
. More specifically, the figure shows a pattern layout having a single main bit line MBL and two sub bit lines SBLs (the single main bit line is formed in the midway of both two sub-bit lines, in parallel).
In
FIG. 6
, in a column sub-selector region, there are two block decode lines BDLs, a block source line BSL, a transistor active region SDG, a plurality of sub-bit lines SBLs, a main bit line MBL, and a plurality of gate wiring layer GLs. The two block decode lines BDLs are made of a first aluminium wiring layer and arranged in parallel to each other in a row direction. The block source line BSL is made of the first aluminum wiring layer and arranged in the row direction. The transistor active region SDG is formed selectively on a surface portion of a semiconductor substrate (alternatively a semiconductor layer or a well region) so as to extend in the row direction. The sub-bit lines SBLs are made of the first aluminium wiring layer and arranged in parallel to each other in a column direction. The main bit line MBL is made of a second aluminium wiring layer and arranged in parallel to the sub-bit line in the column direction. The gate wiring layers GLs are made of a polysilicon wiring layer and arranged in the column direction.
In this layout, a single active region SDG is constituted of adjacent two block selection transistors BSTs. The adjacent two block selection transistors BSTs share a common drain region. In addition, the sub-bit lines SBLs are extended in the column direction from above the corresponding source regions of the active regions SDGs. Each of the source regions is connected to the sub-bit line SBL at a contact portion
53
.
Furthermore, the main bit line MBL is extended from above the common drain region of the active regions SDGs in the column direction. The main bit line MBL is connected to the common drain region by way of a connection line
54
. More specifically, the connection line
54
is made of the first aluminium wiring layer and arranged above the common drain region. The common drain region and the connection line
54
are connected with each other at a contact portion
55
. The connection line
54
is connected to the main bit line MBL through a via hole (through hole)
56
.
The gate wiring layers GL are formed so as to extend in the column direction above channel regions formed between the
Atsumi Shigeru
Tanzawa Toru
Umezawa Akira
Yamada Seiji
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Le Vu A.
Nguyen Vanthu
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