Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-09-09
2001-07-17
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06262449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a random access memory (DRAM) device and, more particularly, To a structure and a method for fabricating an array of DRAM cells having pillar-shaped stacked capacitors with increased capacitance.
2. Description of the Prior Art
Dynamic random access memory (DRAM) circuits are used extensively in the electronic industry, and particularly in the computer industry for storing binary information. The DRAM circuit consists of an array of individual memory cells, each cell consisting of a single pass transistor, usually a field effect transistor (FET), and a storage capacitor. Generally, peripheral row decoder circuits are used to select and access the memory cells via the word lines and pass transistors, and column decoder and read/write circuits are used to store and retrieve binary information in the form of charge on the storage capacitor.
In recent years there has been a dramatic increase in the number of memory cells on a DRAM chip. For example, the cell count on a chip is currently about 64 million, and is expected to reach about 256 million cells (bits) by the year 1998. This increase in the number of cells on a DRAM chip is also expected to increase by a factor of 4 about every 3 years for the foreseeable future. This increase in cell density is a result of down sizing of the individual devices with resulting increase in device packing density. The reduction in device size was achieved predominantly by recent advances in high resolution photolithography, directional (anisotropic) plasma etching and other semiconductor technology innovations, such as forming self-aligning structures, shallow implantations, and similar techniques. However, this device down sizing is putting additional demands on the electrical requirements of the semiconductor devices. For example, the rapid increase in the number of cells on the DRAM chip and the corresponding decrease in physical size of the capacitor has made it increasingly difficult to store sufficient charge on the storage capacitor to maintain an acceptable signal-to-noise level. Also, if the value of the capacitance is not maintained, then these volatile storage cells also require more frequent refresh cycles to maintain the charge on the capacitor.
Because the storage capacitor must occupy an area limited by the cell size, so as to accommodate the array of capacitors on the chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the lateral area that the capacitor occupies on the substrate surface.
One proposed method is to form a trench capacitor by etching trenches in the semiconductor substrate, but unfortunately, as the cell area decreases area it becomes increasing difficult to built the FET and the capacitor in the same substrate cell area. An alternative approach is to use stacked capacitors that are formed on the surface over the FET and within the cell area. These stacked capacitors have received considerable interest in recent years because of the variety of ways that its shape can be controlled in the third dimension to increase the capacitance surface area without increasing the area it occupies on the substrate. Many three-dimensional stacked capacitors having various shapes have been reported in the recent literature, such as fin-shaped, conical shaped, fork-shaped, and the likes have been reported in which the bottom electrode is patterned over the cell area. For example, one method for forming a DRAM device having fork-shaped is described by Y. Park, et al, U.S. Pat. No. 5,332,685, in which contact plugs are formed concurrent for the bottom electrodes of the stacked capacitors and the bit line interconnects, and then both the capacitors and bit lines are formed adjacent to each other. This, however, restricts the capacitor area and necessitates the need for design ground rules that limit the cell area.
On future DRAM devices with very high cell density, it becomes increasingly difficult to align and pattern the capacitor electrode over the cell area that provide sufficient increase in capacitance. Therefore, there is still a very strong need in the semiconductor industry to provide alternative methods for making stacked capacitors that occupy even smaller lateral area on the substrate while providing sufficient capacitance to satisfy the above sign-to-noise ratio requirements.
SUMMARY OF THE INVENTION
The present invention is directed to a DRAM cell structure and a method of fabrication of a pillar-shaped capacitor bottom electrode which also forms the electrode connection to the node contact area of the FET in each cell. The invention utilizes the sidewall areas on the pillar-shaped bottom electrode
ode connection between the FET gate electrodes and word lines to further increase the capacitor area, and thereby provide more capacitance.
It is therefore a principal object of this invention to provide a dynamic random access memory (DRAM) device having stacked capacitor with pillar-shaped bottom electrodes that extend vertically upward and which also serves as the capacitor node contact.
It is another object of the present invention to fabricate these stacked capacitors using a single masking step to form the bottom electrode, and minimize the ground rule tolerances.
It is still a further object of the invention to provide this new stacked capacitor using a simple manufacturing process with good reliability at low cost.
The method for forming the array of DRAM cells having these new pillar-shaped capacitors begins by forming on said semiconductor substrate, typically composed of a lightly P
−
doped single crystalline silicon, field oxide areas that surround and electrically isolate device areas in which are built the pass transistors, which are usually N-channel FETs. The FETs gate electrodes are formed by depositing and patterning a first polysilicon layer on the device areas, and forming concurrently and from the same polysilicon layer, word lines elsewhere on the field oxide areas. Typically the first polysilicon layer is doped with an N-type conductive dopant, such as arsenic (As) or phosphorus (P). Lightly doped source/drain areas are formed in the device areas adjacent to the gate electrodes, usually by ion implanting arsenic (As
75
) or phosphorus (P
31
). Sidewall spacers are then formed on the gate electrodes by depositing and anisotropically etching back an insulating layer, such as a chemically vapor deposited (CVD) silicon oxide (SiO
2
). A second ion implantation is then used to form the source/drain contact areas for the N-FETs.
Pillar shaped stacked capacitors, by the method of this invention, are now formed over and are electrically connected to form the capacitor node contact to one of the two source/drain contact areas of each field effect transistors in the array of device areas. A first insulating layer is deposited over the patterned first polysilicon layer, and then a much thicker second insulating layer is deposited on the first insulating layer. The first insulating layer is composed of silicon nitride (Si
3
N
4
) and is later used as an etch stop layers and insulating layer. The thick second insulating layer is preferably composed of a CVD silicon oxide or alternatively a borophosphosilicate glass (BPSG). Node contact openings are anisotropically etched in the second and first insulating layers to the FET source/drain contact areas, thereby forming node contact openings having essentially vertical sidewalls. A conformal N
+
in situ doped second polysilicon layer is deposited, such as by low pressure CVD (LPCVD), thereby filling the node contact openings, and also forming a uniformly thick second polysilicon layer elsewhere on the second insulating layer. The second polysilicon layer is then thermally oxidized to the top surface of the second insulating layer, while leaving unoxidized the second polysilicon layer in the node contact openings, and thereby forming the pillars-shaped capacitor bottom electrodes having essentially vertical sidewalls and also s
Lu Chih-Yuan
Tseng Horng-Huei
Ackerman Stephen B.
Cao Phat X.
Chaudhuri Olik
Saile George O.
Vanguard International Semiconductor Corporation
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