Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-06-29
2001-07-31
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S100000, C711S104000, C711S105000, C365S203000, C365S235000
Reexamination Certificate
active
06269430
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87119245, filed Nov. 20, 1998, the fill disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention:
This invention relates to a method for controlling the process of writing data to a memory, and more particularly, to a method for controlling the process of writing data sent by a central processing unit (CPU) to a memory by using a CPU interface.
2. Description of Related Art:
The performance of a computer has been improved lately through a faster CPU and advances in other, associated components and peripherals. A random access memory (RAM), one of the major devices within a computer system for accessing data, and the method for controlling the memory circuit have also advanced to provide a faster data access. The RAM itself has been gradually improved in various forms, such as the dynamic RAM (DRAM), the fast page mode (FPM) DRAM, extended data out (EDO) DRAM, and the most recent, synchronized DRAM (SDRAM).
The schematic structural and functional connections between a CPU and a memory circuit in a conventional computer system are shown in FIG.
1
.
Referring to
FIG. 1
, the memory circuit
140
includes a memory control circuit
122
and a memory
130
that further contains memory modules
131
,
132
,
133
and
134
. While the computer is operating, the data and programs used by the CPU
110
are stored in the memory
130
, which the CPU can access through a CPU interface circuit
121
and the memory control circuit
122
. For most computers, the memory control circuit
122
and the CPU interface circuit
121
are normally built into one integrated circuit (IC), which is usually the chipset of a computer mainboard. The memory modules
131
,
132
,
133
and
134
are individually assembled onto the computer mainboard.
When the CPU
110
needs access to the memory
130
, for reading or writing data, a certain control method is used to ensure that the request data are transferred correctly. A conventional method for controlling the access to the memory is illustrated by using a time-sequential diagram in FIG.
2
.
In
FIG. 2
, the width of each longitudinal column represents the period of the system clock built in the computer. The transversal items of the time-sequential diagram represent the signals over different signal lines between the CPU and the memory of a computer system for handling memory access and data processing. The CCLK is the system clock signal. The {overscore (ADS)}, access request, is used by the CPU
110
for sending an access request, wherein either a read request or a write request is sent if the signal on the {overscore (ADS)} is low. The DRDY, data ready, is used to confirm that the data currently transferred through the data bus are valid. The HD, host data, is used to transfer data toward and out from the CPU
110
. The {overscore (DADS)} carries a signal sent by the CPU interface
121
corresponding to the access request sent by the CPU
110
. The SCMD consists of several signal lines for the memory control circuit
122
to send commands, such as activating a memory page or pre-charging a memory page, to a SDRAM
130
. The MD, the memory data, is the data bus connected to the memory control circuit
122
. The RSTB, the read strobe, confirm that the data read from the memory
130
are valid. The WSTB, the write strobe, shows that the data transferred by the MD is currently written to the memory
130
.
Referring to
FIG. 2
together with
FIG. 1
, CPU
110
sends out a read request
211
at time T1, and later on, sends out a write request
212
at time T4, both through the signal line {overscore (ADS)}, wherein both signals are received by the CPU interface
121
. After the CPU interface
121
receives signal
211
, it sends out a read request
241
to the memory control circuit
122
through the signal line {overscore (DADS)}. By executing the commands
251
sent through the signal line SCMD, the memory control circuit
122
provides requested data through the signal line MD in a latency of about two clock cycles. As shown in
FIG. 2
, there are four sets of requested data that are transferred to the CPU interface
121
through the signal line MD. The CPU interface
121
then sends the requested data to the CPU
110
through the signal line HD after another two clock cycles.
After the read request is executed completely, the CPU
110
sends out the data to be written to the memory
130
at the time T16 by using the signal line HD. After the CPU interface
121
receives the data, it sends a write request
242
to the memory control circuit
122
through the signal line {overscore (DADS)}. If the location where the data are to be written is not on the currently activated memory page, the memory control circuit
122
has to send commands through the signal line SCMD before the write request
254
is executed. The commands executed before command
254
include command
252
, to pre-charge the desired memory page, and command
253
, to activate the desired memory page.
According to the foregoing, the CPU interface
121
does not send out the write request
242
to the memory control circuit
122
until it receives data that are to be written. Once the memory control circuit
122
receives the write request
242
from the CPU interface
121
, it has to execute commands
252
and
253
before it actually sends out the command
254
, which actually writes data to the memory
130
, if the desired memory location is not activated while the write request is received by the memory control circuit
122
. Since a simple task, writing data to a memory location, takes about 9 clock cycles by using the conventional method, by which expanse of time the performance of the computer is obviously limited.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for controlling the writing process to reduce the writing latency.
It is another an objective of the present invention to provide a method for writing data sent by a central processing unit (CPU) to a memory through the control of a CPU interface to reduce the writing latency.
In accordance with the foregoing and other objectives of the present invention, the method of the invention allows a CPU interface to control the writing process, including receiving a write request and data from a CPU and then writing the data to a memory of a memory circuit. After the CPU interface receives a write request from the CPU, the CPU interface sends a dummy request to the memory control circuit to pre-charge and activate the designative memory page of the memory circuit before the data is sent to the memory circuit. Since the designative memory page is always pre-charged and activated while the data is received at the memory control circuit, the memory control circuit sends only a write commands to the memory for writing the data to the memory without further pre-charging and activating the designative memory page. Therefore, the total number of clock cycles required for processing a write request is shortened.
More specifically, the method of the invention starts with a write request that is sent from a CPU to a CPU interface, wherein the write request consists of address information and data information. The address information carries a designative memory address where the data are to be written. The data information contains a value equal to the length of the data to be written to the designative memory page. After the CPU interface receives the write request, it sends a dummy request to the memory control circuit of a memory circuit. The dummy request carries an address information exactly the same as that of the write request and a zero-value data information. While the data to be written is sent from the CPU to the CPU interface, the memory control circuit pre-charges and activates a designative memory page according to the address information within the dummy request. Hence, while the data is sent from the CPU i
Chen Chia-Hsin
Chiu You-Ming
Lai Jiin
Huang Jiawei
J.C. Patents
Thai Tuan V.
VIA Technologies Inc.
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