Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-08-01
2001-07-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S189050, C365S189070
Reexamination Certificate
active
06259639
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device on which a large-scale memory circuit is mounted.
2. Description of the Prior Art
With recent improvements in the semiconductor machining technology, it has become possible to mount a large-scale memory cell unit on semiconductor integrated circuit devices. In general, large-scale memory cell units have a larger packaging density than logic circuits, and therefore can be easily failed components. Conventionally, repair techniques of preparing redundant areas, and making each of the redundant areas take the place of a defective word or bit in a memory cell, which is found by a post-manufacturing test, have been used as a method of repairing defective parts of a memory cell unit during manufacturing. Repair techniques include a fuse-type memory repair technique of physically opening the circuit formed by a fuse corresponding to a defective part to disconnect the defective part from a memory cell unit using laser light, and substituting a redundant unit for the defective part. Japanese patent application publication (TOKKAIHEI) No. 4-372798 discloses such a repair method of repairing defective parts in a memory cell unit located in a prior art semiconductor integrated circuit device.
A problem with a prior art semiconductor integrated circuit device constructed as above is that the use of a fuse-type memory repair technique of physically opening the circuit formed by a fuse corresponding to a defective part to disconnect a defective part from a memory cell unit disposed in a large-scale memory increases the manufacturing cost because of a physical post-manufacturing wiring and testing of the large-scale memory.
SUMMARY OF THE INVENTION
The present invention is proposed to solve the above problem. It is therefore an object of the present invention to provide a semiconductor integrated circuit device capable of repairing defective parts in a large-scale memory cell unit mounted thereon without increasing the manufacturing cost.
In accordance with one aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a memory cell unit having a normal port via which a normal read/write operation is performed, and a test port intended for tests, via which data can be read out of the memory cell unit; a data latch unit for temporarily latching write data, which is written into the memory cell unit by way of the normal port; a comparator for reading the data, which has been written into the memory cell unit by way of the normal port, from the memory cell unit by way of the test port, and for comparing the read data with the original write data latched by the data latch unit; a redundant unit for latching the write data to take the place of the memory cell unit when the comparator detects a mismatch between the data read by the comparator and the write data latched by the data latch unit; and an address holding unit for holding information on an address identifying a location of the memory cell unit into which the write data has been written when the comparator detects a mismatch between the data read by the comparator and the write data.
In accordance with a preferred embodiment of the present invention, the data latch unit includes a plurality of data latches each for temporarily latching write data, which is written into the memory cell unit by way of the normal port. Further, when reading data from a location at an address, in which a mismatch was found by the comparator, of the memory cell unit for the first time, the device furnishes write data latched by a corresponding one of the plurality of data latches, and, from then on, when performing a write/read operation to access the address, directly accesses the redundant unit that is holding the write data associated with the address stored in the address holding unit without performing a comparison by means of the comparator.
In accordance with another preferred embodiment of the present invention, the data latch unit includes only one data latch for temporarily latching write data, which is written into the memory cell unit by way of the normal port. When the write data is written into the memory cell unit, the comparator compares the write data latched by the data latch with corresponding data read out of the memory cell unit, and, if the comparator detects a mismatch between them, the redundant unit latches the write data and the address holding unit latches an address identifying a location of the memory cell unit into which the write data has been written. After that, when the comparator performs a comparison associated with the same address and then detects a match, the address is cleared from the address holding unit or the address can be overwritten with a new one, and the write data is cleared from the redundant unit or the write data can be overwritten with new data.
In accordance with another preferred embodiment of the present invention, the data latch unit includes only one data latch for temporarily latching write data, which is written into the memory cell unit by way of the normal port. When the write data is written into the memory cell unit, the redundant unit can latch the write data and the address holding unit can latch an address identifying a location of the memory cell unit into which the write data has been latched. The comparator then compares the write data latched by the data latch with corresponding data read out of the memory cell unit, and, if the comparator detects a mismatch between them, the redundant unit keeps holding the write data latched thereinto and the address holding unit keeps holding the address latched thereinto. Otherwise, the address is cleared from the address holding unit or the address can be overwritten with a new one, and the write data is cleared from the redundant unit or the write data can be overwritten with new data.
Preferably, the semiconductor integrated circuit device can further comprise an address decoder unit for decoding an incoming address applied thereto when performing a read/write operation, the address decoder unit including a first decoder for activating word lines connected to the redundant unit, and a second decoder for activating word lines connected to the memory cell unit. Further, the address holding unit can determine whether or not it is holding an address equal to the incoming address, and, if the address holding unit determines that it is holding an address equal to the incoming address, the first decoder activates a corresponding word line connected to the redundant unit, and, otherwise, the second decoder activates a corresponding word line connected to the memory cell unit.
In accordance with another preferred embodiment of the present invention, when the redundant unit does not have free space enough to take the place of the memory cell unit, the device asserts a full flag signal. As an alternative, when the redundant unit does not have free space enough to take the place of the memory cell unit and the comparator detects a mismatch between write data latched by the data latch unit and corresponding data read out of the memory cell unit, the device asserts an overflow signal.
In accordance with another aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a memory cell unit having a normal port via which a read/write operation is performed, and a test port intended for tests, via which data can be read out of the memory cell unit; a data latch unit for temporarily latching write data, which is written into the memory cell unit by way of the normal port; a comparator for reading the data, which has been written into the memory cell unit by way of the normal port, from the memory cell unit by way of the test port, and for comparing the read data with the original write data latched by the data latch unit bit by bit; an address and bit information holding unit for, if the comparator detects a mismatch between the data read by the compa
Burns Doane , Swecker, Mathis LLP
Lam David
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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