Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-05-07
2001-01-09
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S637000, C438S675000, C438S784000
Reexamination Certificate
active
06171944
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to methods and tools used in modification, debugging and failure analysis of integrated circuit (IC) products or devices in the semiconductor industry, and more particularly to a method for bringing up lower level metal nodes of multi-layered IC devices in a manner that requires fewer steps than the prior art and is substantially more reliable than the prior art, and to an article produced by this method.
Bringing up lower level metal nodes of multi-layered IC devices is necessary for IC device modification or re-routing, and is very useful in debugging and failure analysis. This task, however, is difficult and tedious, especially when desired or target metal nodes or layers are buried under other higher level or non-target metal nodes or layers. As a result, not only are target nodes difficult to access, but also undesired shorts are difficult to prevent. The user avoids shorts between the target and non-target nodes by insulating the non-target nodes from the target node with an insulator material before bringing up the target node. To further complicate matters, as the number of metal layers increases, the lower level metal nodes become increasingly thinner and the node population becomes increasingly more dense. As can be expected, this increases the difficulty and decreases the success rate. Overall, the prior art method is problematic because it is unduly time-consuming and has a low success rate.
The conventional and most well known method for bringing up lower level target nodes is a four-step process using a focused ion beam (FIB) system. In summary, the first step is to expose the target metal node by milling. In most cases, this exposing step also exposes other nearby non-target metal nodes due to circuit density. The second step is to deposit insulative material to isolate the exposed non-target nodes, preventing them from shorting one another or the target node during the fourth step, the metal deposition step. FIB induced insulator deposition (the second step) provides two kinds of materials—a directly deposited or primary material within an ion-beam scan pattern and an indirectly deposited or secondary material due to the fringe energy of the ion beam. The third step is to mill away the directly deposited material of step two. The fourth step is to deposit metal, typically platinum or tungsten, to bring up the target metal node.
The prior art method steps and problems will now be described in more detail.
In the first step (FIG.
1
), following the usual, customary and widely practiced analytical process, the user mills down through the obstructing or non-target metal layers
120
and the insulative inter layer dielectrics (ILD)
130
, exposing these layers
120
and
130
, and stops part way through the last ILD layer
130
′ in the customary manner just above the target metal layer
140
. (For clarity of illustration, multiple layers typically above
130
′ and
140
have been omitted from the drawing figures.)
In the second step (FIG.
2
), an ion beam deposits insulator material
160
to isolate the exposed non-target nodes
120
preventing them from shorting one another or the target node
140
during the forth step (FIG.
4
), the metal deposition step. As stated, FIB induced insulator deposition provides two kinds of materials—a directly deposited or primary material
150
within an ion-beam scan pattern and an indirectly deposited or secondary material
160
due to the fringe energy of the ion beam. Tetraethyl Orthosilicate (TEOS) is the insulator material typically used and Gallium (Ga) is the ion source typically used to decompose TEOS gas to form and deposit the TEOS insulator material. Material analysis shows that the Ga content, due to Ga ion implantation, in the directly deposited material
150
is twice the amount of Ga content in the indirectly deposited material
160
. As a result, the directly deposited material
150
is generally conductive while the indirectly deposited material
160
is insulative. Because an insulator is desired, the user, in known fashion, reduces the degree of Ga ion implantation in the insulator material by setting the Ga ion-beam to a low beam current level. This maximizes any insulative properties and minimizes any conductive properties. The ion-beam scan pattern is scanned such that the indirectly deposited or secondary material
160
insulates the non-target metal nodes
120
from the deposited metallic material
180
of Step
4
(FIG.
4
).
As stated, because the primary intent of Step
2
is to insulate the non-target nodes
120
, the directly deposited or primary material
150
is regarded as an undesired byproduct of the deposition and is milled away in Step
3
(FIG.
3
.).
Thus, in the third step (FIG.
3
.), the user mills through the primary material
150
eliminating it entirely, and continues milling through the remainder of the ILD layer
130
′ that was partially preserved in Step
1
(FIG.
1
), stopping at the target metal node or layer
140
. As is well known, the user observes the procedure via a secondary electron image. Insulative material produces a dark image; conductive material produces a light image. The user knows when to stop because the primary material
150
being conductive produces a light image, the ILD material
130
′ being insulative produces a dark image, and the target metal layer
140
being conductive produces a light image. In other words, the secondary electron image goes from light (primary material) to dark (ILD) to light (target metal layer). This is the most difficult step due to poor contrast between underlying metal and deposited insulator material. This step may require practice on a practice chip which can make the overall procedure tedious and unduly time consuming.
The fourth step is to deposit metal
180
, typically platinum or tungsten, to bring up the target metal node
140
.
Excessive time consumption, difficulty, and a disappointingly low success rate are the main disadvantages of the prior art. The prior art has attempted to address these concerns but has fallen short of producing desired and reliable results.
A need therefore remains for a method for bringing up lower level target nodes in a manner that is time efficient, simple, and reliable, and for a reliable node structure resulting from the method. Such a node structure needs to have an easily and reliably generated conductive portion which is insulated from surrounding non-target metal layers. Also, the method must sustain device functionality.
SUMMARY OF THE INVENTION
The present invention meets the above needs and objectives with a new and improved method for bringing up a lower level metal node, and a resulting node structure that reliably brings up the lower level target metal node. This node structure has a sufficiently conductive core connected to the target metal node and a sufficiently insulative sheath preventing surrounding non-target metal nodes from shorting one another, the conductive core, or the target metal node.
In the preferred embodiment, the method according to the present invention requires only two steps: first, exposing the target metal node by milling down to it; and second, depositing Ga implanted TEOS material directly onto the target node to create a node structure having a substantially conductive core and a substantially insulative sheath. The resulting node structure extends from the target node upwardly such that the conductive core makes electrical contact with the target node. The insulative sheath prevents surrounding non-target metal nodes from shorting one another, the conductive core, or the target metal node.
The present invention provides a more expedient and more reliable two-step method over the four-step method of the prior art. In the first step of the present invention, the user mills down to the target metal node or layer unconcerned about surrounding non-target metal nodes. After depositing Ga implanted TEOS material onto the target node in the manner taught herein, the user simply p
Gilfeather Glen
Li Xia
Advanced Micro Devices , Inc.
Lin Yung A.
Sawyer Law Group LLP
Wilczewski Mary
LandOfFree
Method for bringing up lower level metal nodes of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for bringing up lower level metal nodes of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for bringing up lower level metal nodes of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2538429