Clock signal generator circuit

Details Clock signal generator circuit Clock signal generator circuit

1999-10-12

2001-06-19

Wamsley, Patrick (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C327S176000, C327S174000, C327S173000

Reexamination Certificate

active

06249150

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clock signal generator circuit, and more particularly to a circuit for generating a sub-clock signal having a predetermined signal width and rising in synchronization with a given main clock signal by use of the given main clock signal and an inverted delay signal to the main clock signal.
Such clock signal generator circuits are, for example, used for generating clock signals from a system clock signal and supplying the generated clock signal to a device such as a synchronous dynamic random access memory which operates in synchronizing with the system clock signal used in a memory system having a synchronous dynamic random access memory.
An example of the conventional clock signal generator circuit is shown in FIG.
8
. The first conventional clock signal generator circuit has a receiver circuit
1
for receiving and waveform-shaping a system clock signal CLK
1
externally inputted so as to generate a waveform-shaped internal signal S
10
. The first conventional clock signal generator circuit also has a delay circuit
50
connected to the receiver circuit
1
for fetching the waveform-shaped internal signal S
10
and delaying and inverting the same to generate an inverted delay signal S
50
. The first conventional clock signal generator circuit also has a NAND gate connected to the receiver circuit
1
and the delay circuit
50
for receiving the internal signal S
10
and the inverted delay signal S
50
to generate a NAND logic signal. The first conventional clock signal generator circuit also has an inverter buffer connected to the NAND gate for receiving the WAND logic signal to invert the same and generate a sub-clock signal CLK
2
c
. The system clock signal is supplied as the clock signal CLKE into the receiver circuit
1
, wherein the system clock signal is supplied from the synchronous dynamic random access memory. The generated sub-clock signal CLK
2
c
is outputted as a time-reference signal for operations of the synchronous dynamic random access memory.
NAND gate and the inverter on the next stage form an AND gate logically, for which reason in the following descriptions, the above NAND gate and the inverter deal with the AND-gate
2
. There is no signal delay in signal transmission in the circuit except when the signal is intentionally delayed as the delay circuit
50
described above. No signal delay is caused in the AND gate
2
and the receiver circuit
1
. The receiver circuit
1
does not play any roll in the operational principal as will be apparent from the operations described blow.
The above clock signal generator operates as follows. With reference to
FIG. 9
which shows a timing chart of the circuit, in an initial state (prior to a time t10), the system clock signal CLK
1
is low level. The internal signal S
10
is low level. The inverted delay signal S
50
is high level. The sub-clock signal CLhc is low level. At the time t10, the internal signal S
10
rises from the low level to high level, whereby one input of the AND gate
2
becomes high level, whilst another input as the inverted delay signal S
50
to the AND gate
2
remains high level. Therefore, the sub-clock signal CLK
2
c
from the AND gate
2
rises from the low level to the high level at the same time when the internal signal S
10
rises to high level.
After the delay time “td” by 11-stages of the delay circuit
50
has passed and the time becomes t11, the internal signal S
10
reaches an output point of the delay circuit
50
, whereby the inverted delay signal S
50
falls from the high level down to the low level, whereby the one input of the AND gate
2
becomes low level, and thus the sub-clock signal CLK
2
c
falls from the high level down to the low level.
Finally, at a time “t12” decided by a high level width of the system clock signal, the internal signal S
10
falls from the high level down to the low level. At a time “t13” delayed by a delay time “td” from the time “t12”, the inverted delay signal S
50
rises from the low level to the high level, whereby the circuit returns into the initial state.
From the externally supplied system clock signal CLK
1
and the inverted delay signal S
50
of the system clock signal CLK
1
, the sub-clock signal CLK
2
c
is generated which rises in synchronizing with the rising of the system clock signal CLK
1
and has a high level width corresponding to the delay time “td”.
In the industrial view point, it is preferable that the clock signal generator circuit is general and applicable to various systems rather than specific to one particular system, because stable supply and mass-production for cost reduction are possible. In the above clock signal generator circuit, however, when the high level width of the system clock signal CLK
1
is narrow or the low level width thereof is narrow, the sub-clock signal may be risen with delay from the rising of the system clock signal. Even if the sub-clock signal is risen at the normal timing without delay, the sub-clock signal is fallen prior to the delay time “td”. Depending upon the system clock signal, the high level width of the sub-clock signal is different from the predetermined or intended width. There was an issue to solve the above problem for responsibility to various system.
With reference again to the timing chart shown in
FIG. 9
, operations from the time “t10” to the time “t13” are operations of an A-system, wherein the sub-clock signal is generated which has the normal rinsing time and the normal high level width by utilizing the clock signal generator circuit. The time sequence of the transitions in level of the system clock signal CLK
1
and the inverted delay signal S
50
in operation of the A-system are as follows.
{circle around (1)} At the time “t10”, the system clock signal CLK
1
is risen.
{circle around (2)} At the time “t11”, the inverted delay signal SSO is fallen.
{circle around (3)} At the time “t12”, the system clock signal CLK
1
is fallen.
{circle around (4)} At the time “t13”, the inverted delay signal S
50
is risen to return into the initial state.
Namely, the high level width of the system clock signal CLK
1
is larger than the delay time “td” of the delay circuit
50
. The next cycle is executed after the inverted delay signal S
50
was returned into high level in the last state of the previous cycle and the delay circuit
50
has re-set into the initial state.
Operations from the time “t20” to the time “t23” in
FIG. 9
are operations of a B-system, wherein the high level width of the system clock signal CLK
1
is shorter than the delay time “td”. In this case, the high level width of the system clock signal CLK
1
is narrow. After the system clock signal or the internal signal S
10
has been risen at the time “t20” and the delay time “td” has passed, and then at the time “t21”, the system clock signal CLK
1
returns from the high level into the low level before the inverted delay signal S
50
is fallen with the delay time “td” at the time “t22”. With reference to
FIG. 9
, when at the time “t20”, the internal signal S
10
is risen from the low level into the high level, then the output sub-clock signal CLK
2
c
is risen form the low level to the high level. After the delay time “td” has passed, at the time “t22”, the inverted delay signal S
50
is fallen from the high level into the low level.
Before the inverted delay signal S
50
is fallen at the time “t22” and the internal signal S
10
inputted into the delay circuit
50
reaches the output point of the delay circuit
50
, at the time “t21” internal signal S
10
is fallen from the high level into the low level, whereby one input of the AND gate
2
becomes low level. Thus, at the same time when the internal signal S
10
is risen, the sub-clock signal CLK
2
c
is fallen from the high level into the low level. At the time “t23” with the delay time “td” from the falling of the internal signal S
10
, the inverted delay signal S
50
is risen from the low level to the high level thereby returning into the initial state.
In this B-system, the high level time period

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