Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1998-10-06
2001-04-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S015000, C438S014000, C438S025000, C438S026000, C438S051000, C438S055000, C438S064000, C438S106000, C438S121000, C257S048000
Reexamination Certificate
active
06218202
ABSTRACT:
The present invention relates in general to the field of semiconductor integrated circuit assembly and testing and more specifically to substantially flat packages standardized for burn-in and testing of devices from a range of semiconductor families, and a method for the fabrication.
BACKGROUND OF THE INVENTION
The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's “law”), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
For semiconductor memory devices, historically the time span of at least three years has been needed between two generations of memory families. The new generation offers a four times larger memory capacity compared to the preceding generation. Again, shrinking circuit feature sizes and more complex memory hierarchies have been the prerequisite of the new product generation—at high development cost for chip design and fabrication processes, coupled with very expensive investment in costly new manufacturing equipment.
A number of technical advances have recently been achieved in an effort to obtain an advantage in this competitive marketplace. Within the semiconductor memory product families, one of the most promising concepts for shrinking the package outline and thus consuming less area when the device is mounted onto the circuit board, has been the so-called “board-on-chip” design replacing the traditional metallic leadframe. Patent application Ser. No. 9702348-5 entitled “Board on Chip—Ball Grid Array Chip Size Package” has been filed by Texas Instruments in Singapore on Jul. 02, 1997. This patent application for memory products successfully approaches the problem of reducing the area requirement by replacing the traditional leaded package design with a solder ball concept. In addition, it offers a reduction in the height requirement by replacing the leadframe-on-chip assembly with a thinner and more flexible board-on-chip design. Using the new concept, a high-density integrated circuit package has been described in patent application Ser. No. 9703963-0 entitled “High Density 3-Dimensional Stacked Ball Grid Array Integrated Circuit Module”, filed by Texas Instruments in Singapore on Nov. 6, 1997. A new modification using thin board-on-chip devices entitled “Thin Board-on-Chip Integrated Circuit Unit” has been submitted by Texas Instruments in Singapore, also in 1997.
It is frustrating, though, that in spite of all this progress so much time and money has to be spent continuously for testing and burning-in each new package and each new device. Required are design and acquisition of dedicated burn-in and test sockets for each different input/output count and each different package configuration; dedicated sockets, boards, trays, tubes and handlers; lack of standardization of equipment and procedures for testing and burn-in; and limited comparison of accumulated data. Due to ever modified package outlines, testing and burn-in remain dedicated fabrication steps with no interchangeablity. Consequently, a need has arisen for package designs and methods of device fabrication that provide simple, low-cost designs for a universal fanout package concept with a configuration suitable for an entire device family. Preferably, these improvements should be accomplished using the installed equipment base so that no investment in new burn-in and testing facilities is needed.
SUMMARY OF THE INVENTION
The present invention comprises the design and manufacturing of integrated circuit packages with universal burn-in and testing features. Patterns of contact pads for electrical connection and patterns of testing pads for electrical characterization are defined so that the testing pads are adapted with location, size, and material composition for an eventual conversion to contact pads after the device has undergone burn-in and testing. The testing pads are preferably located remote from the contact pads. The present invention also defines the package design rules to permit universal use of burn-in sockets and boards, test handlers and boards, and transport trays and tubes for entire product families. These package design rules use the maximum number of input/output terminals expected for the product family and assign the terminals for the configuration of the specific capacity and architecture of the device, with equal functions assigned to equal terminals and unused terminals remaining unassigned.
It is an object of the present invention to provide a methodology for universal testing and burn-in of a complete family of semiconductor devices with devices of different input/output configuration.
Another object of the present invention is to provide a low-cost method for designing and fabricating the universal package features for testing.
Another object of the present invention is to increase the flexibility of device packages by adapting design and process features so that testing pads can optionally be converted to contact pads.
Another object of the present invention is to provide a design method of electrical connections, as well as low-cost process for fabrication, for parts of small outline packages of memory products suitable for producing stacked memory modules.
Another object of the present invention is to minimize the cost of capital investment and to use the installed fabrication equipment base.
Another object of the present invention is to provide reliability assurance for the finished product through in-process control at no extra cost.
These objects have been achieved by the package designs of the invention, the universal testing and burn-in concept for entire product families, and a mass production process. Various modifications have been employed for the package configurations and the assembly of packages and modules.
In one embodiment of the invention, a pattern of contact pads for electrical connection and a pattern of testing pads for electrical characterization are designed so that the testing pads have a size, location and material composition suitable for converting them to contact pads after the device has been burnt-in and electrically characterized.
In another embodiment of the invention, stacked modules of such devices have been created.
In another embodiment of the invention, the testing pads remain unconverted to contact pads.
In yet another embodiment of the invention, a standard auxiliary substrate, compatible with test sockets of the thin small-outline package (TSOP) families, has been manufactured to convert board-on-chip ball grid array BOC-BGA™ products to the installed socket facilities.
In another embodiment of the invention, a universal package handles the entire family of 64 Mbit DRAM, SDRAM, and EDO devices in the x4, x8, and x16 organizations.
The technical advance represented by the invention, as well as the objects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
REFERENCES:
patent: 5289631 (1994-03-01), Koopman et al.
patent: 5290710 (1994-03-01), Haj-Ali-Ahmadi et al.
patent: 5525545 (1996-06-01), Grube et al.
patent: 5541525 (1996-07-01), Wood et al.
patent: 5806181 (1998-09-01), Khandros et al.
patent:
Chan Min Yu
Tey Kim Hoch
Toh Jeffrey Tuck Fock
Yew Chee Kiang
Honeycutt Gary C.
Lee Jr. Granvill D
Navarro Arthur I.
Smith Matthew
Telecky Fred
LandOfFree
Semiconductor device testing and burn-in methodology does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device testing and burn-in methodology, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device testing and burn-in methodology will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2537683